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49LF002B Datasheet

Part NameDescriptionManufacturer
49LF002B 2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash SST
Silicon Storage Technology SST
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PRODUCT DESCRIPTION
The SST49LF00xB flash memory devices are designed to interface with host controllers (chipsets) that support a low pin-count (LPC) interface for BIOS applications. The SST49LF00xB devices comply with Intel’s LPC Interface Specification 1.1, supporting single-byte Firmware Memory
and LPC Memory cycle types.
The SST49LF00xB devices are backward compatible to the SST49LF00xA Firmware Hub and the SST49LF0x0A LPC Flash. In this document, FWH mode in the SST49LF00xA specification is referenced as the Firmware Memory Read/Write cycle and LPC mode in the SST49LF0x0A specification is referenced as the LPC Memory Read/Write cycle. Two interface modes are supported by the SST49LF00xB: LPC mode (Firmware Memory and LPC Memory cycle types) for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.

FEATURES:
• 2 Mbit, 3 Mbit, or 4 Mbit SuperFlash memory array for code/data storage
– SST49LF002B: 256K x8 (2 Mbit)
– SST49LF003B: 384K x8 (3 Mbit)
– SST49LF004B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.1
– Supports Single-Byte LPC Memory and Firmware Memory Cycle Types
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 16 KByte overlay blocks for SST49LF002B
– Uniform 64 KByte overlay blocks for SST49LF003B/004B
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST49LF002B: 4 seconds (typical)
SST49LF003B: 6 seconds (typical)
SST49LF004B: 8 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) interface mode for in-system operation
– Parallel Programming (PP) mode for fast production programming
• LPC Interface Mode
– LPC bus interface supporting byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block Write-Lock and Lock-Down protection
– JEDEC Standard SDP Command Set
– Data# Polling and ToggleBit for End-of-Write detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data I/O interface
– Supports fast In-System or PROM programming for manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC all devices
For SST49LF004B only:
– 40-lead TSOP (10mm x 20mm)
• All non-Pb (lead-free) devices are RoHS compliant

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