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54ACT109F Datasheet

Part NameDescriptionManufacturer
54ACT109F Dual JK Positive Edge-Triggered Flip-Flop National-Semiconductor
National ->Texas Instruments National-Semiconductor
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General Description
The ’AC/’ACT109 consists of two high-speed completely in dependent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’AC/’ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
  LOW input to SD (Set) sets Q to HIGH level
  LOW input to CD (Clear) sets Q to LOW level
  Clear and Set are independent of clock
  Simultaneous LOW on CD and SD makes both Q and Q HIGH

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ’ACT109 has TTL-compatible inputs
■ Standard Military Drawing (SMD)
   — ’AC109: 5962-89551
   — ’ACT109: 5962-88534

 

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