datasheetq language:
Home >>> ST-Microelectronics >>> 74ACT138M Datasheet

74ACT138M Datasheet

Part Name74ACT138M ST-Microelectronics
STMicroelectronics ST-Microelectronics
Description3 TO 8 LINE DECODER (INVERTING)
74ACT138M Datasheet PDF : 74ACT138M pdf     
  
74ACT138B image

DESCRIPTION
The 74ACT138 is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems.

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS
   VIH = 2V (MIN.), VIL = 0.8V (MAX.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS:
   tPLH = tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138
■ IMPROVED LATCH-UP IMMUNITY

 

Share Link : ST-Microelectronics

Searches related to 74ACT138M description



Language : 한국어   日本語   русский   简体中文   español
@ 2015 - 2017  [ Home  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]