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ADS6422IRGC25 Datasheet

Part NameDescriptionManufacturer
ADS6422IRGC25 QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE TI
Texas Instruments TI
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DESCRIPTION
The ADS6424/ADS6423/ADS6422 (ADS642X) is a family of high performance 12-bit 105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS642X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
ADS642X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

FEATURES
• 12-Bit Resolution With No Missing Codes
• Simultaneous Sample and Hold
• 3.5dB Coarse Gain and upto 6dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs With Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400
   mVPP
• Internal Reference With External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 64 QFN Package (9 mm × 9 mm)
• Pin Compatible 14-Bit Family (ADS644X -
   SLAS531A)
• Feature Compatible Dual Channel Family
   (ADS624X - SLAS542A, ADS622X - SLAS543A)

APPLICATIONS
• Base-station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

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