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IS61NSCS25672 Datasheet

Part NameDescriptionManufacturer
IS61NSCS25672 ΣRAM 256K x 72, 512K x 36 18Mb Synchronous SRAM ISSI
Integrated Silicon Solution ISSI
Other PDF  not available.
IS61NSCS25672 image

SigmaRAM Family Overview
The IS61NSCS series ΣRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. The implementations are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• JEDEC SigmaRam pinout and package standard
• Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max)
• Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical
• LVCMOS-compatible I/O interface
• Common data I/O pins (DQs)
• Single Data Rate (SDR) data transfers
• Pipelined (PL) read operations
• Double Late Write (DLW) write operations
• Burst and non-burst read and write operations, selectable via dedicated control pin (ADV)
• Internally controlled Linear Burst address sequencing during burst operations
• Burst length of 2, 3, or 4, with automatic address wrap
• Full read/write coherency
• Byte write capability
• Two cycle deselect
• Single-ended input clock (CLK)
• Data-referenced output clocks (CQ/CQ)
• Selectable output driver impedance via dedicated control pin (ZQ)
• Echo clock outputs track data output drivers
• Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package


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