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IS61SP12836 Datasheet

Part NameDescriptionManufacturer
IS61SP12836 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM ICSI
Integrated Circuit Solution Inc ICSI
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DESCRIPTION
The ICSI IS61SP12836 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the i486™, Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 131,072 words by 36 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass  through registers controlled by a positive-edge-triggered single clock input.

FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-pin LQFP and 119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode

 

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