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PA7128JI-20 Datasheet

Part NameDescriptionManufacturer
PA7128JI-20 Programmable Electrically Erasable Logic Array International-Cmos
International Cmos Technology 
Other PDF  not available.
PA7128JI-20 image

General Description
The PA7128 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

■ CMOS Electrically Erasable Technology
    − Reprogrammable in 28-pin DIP, SOIC and PLCC packages
■ Versatile Logic Array Architecture
    − 12 I/Os, 14 inputs, 36 registers/latches
    − Up to 36 logic cell output functions
    − PLA structure with true product-term sharing
    − Logic functions and registers can be I/O-buried
■ Flexible Logic Cell
    − Up to 3 output functions per logic cell
    − D,T and JK registers with special features
    − Independent or global clocks, resets, presets, clock polarity and output enables
    − Sum-of-products logic for output enables
    − As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)
    − Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85 °C temperatures
■ Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications
    − Integration of multiple PLDs and random logic
    − Buried counters, complex state-machines
    − Comparitors, decoders, other wide-gate functions
■ Development and Programmer Support
    − ICT PLACE Development Software
    − Fitters for ABEL, CUPL and other software
    − Programming support by ICT PDS-3 and other popular third-party programmers.


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