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PA7540 Datasheet

Part NameDescriptionManufacturer
PA7540 PA7540 PEEL Array™ Programmable Electrically Erasable Logic Array Anachip
Anachip Corporation Anachip
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General Description
The PA7540 is a member of the Programmable Electrically Erasable Logic (PEELô) Array family based on ICTís CMOS EEPROM technology. PEELô Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for todayís programmable logic designs.

Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried

Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide gate functions

High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures

CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages
- Optional JN package for 22V10 power/ground compatibility

Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets, clock polarity and output enables
- Sum-of-products logic for output enables

Development and Programmer Support
- Anachipís WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party programmers

 

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