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SDA5648 Datasheet

Part Name
Description
MFG CO.
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Functional Description
The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data of the PDC system from the data lines broadcast during the vertical blanking interval of a standard video signal.

Features
● Single-chip receiver for PDC data, broadcast either
    – in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or
    – in dedicated line no. 16 of the vertical blanking interval (VPS)
● Reception of Unified Date and Time (UDT) broadcast in BDSP 8/30/1
● Low external components count
● On-chip data and sync slicer
● I2C-Bus interface for communication with external microcontroller
● Selection of PDC/VPS operating mode software controlled by I2C-Bus register
● Pin and software compatible to VPS Decoder SDA 5642
● Supply voltage: 5 V ± 10 %
● Video input signal level: 0.7 Vpp to 1.4 Vpp
● Technology: CMOS
● Package: P-DIP-14-3 and P-DSO-20-1
● Operating temperature range: 0 to 70 °C

 

Part Name
Description
PDF
MFG CO.
Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
Infineon Technologies
Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
Infineon Technologies
VPS/PDC-Plus Decoder
Micronas
VPS / PDC-plus Decoder
Infineon Technologies
On-chip Flash program memory with in-system programming
Macronix International
Sample Program (Remote Control Transmission/Reception)
Renesas Electronics
Dual standard PDC decoder
Philips Electronics
Video Decoder and System Controller (with JTAG)
Motorola => Freescale
VPS / PDC Slicer IC
SANYO -> Panasonic
Calculating Program Memory Checksums Using a PIC16F87X
Microchip Technology

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