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[ACTEL]

General Description
ProASIC3, the third-generation Family of Actel Flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® Family. Nonvolatile Flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

Features and Benefits
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os

Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing

High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI (except A3P030)

In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except A3P030 and ARM®- enabled ProASIC®3 devices) via JTAG (IEEE 1532– compliant)
• FlashLock® to Secure FPGA Contents

Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches

High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization

Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os (A3P030 only)
• Programmable Output Slew Rate (except A3P030) and Drive Strength
• Weak Pull-Up/Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages Across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL (except A3P030)
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback, Multiply/Divide, Delay Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• CoreMP7Sd (with debug) and CoreMP7S (without debug

SRAMs and FIFOs (except A3P030)
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 Organizations Available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz

Soft ARM7™ Core Support in M7 ProASIC3 Devices
• CoreMP7Sd (with debug) and CoreMP7S (without debug)

Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock® Designed to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC®3E Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz

ARM® Processor Support in ProASIC3E FPGAs

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Features and Benefits
High Capacity
   • 15 k to 1 M System Gates
   • Up to 144 kbits of True Dual-Port SRAM
   • Up to 300 User I/Os
Reprogrammable Flash Technology
   • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
      Process
   • Instant On Level 0 Support
   • Single-Chip Solution
   • Retains Programmed Design when Powered Off
High Performance
   • 350 MHz System Performance
   • 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
   • ISP Using On-Chip 128-Bit Advanced Encryption Standard
      (AES) Decryption (except ARM®-enabled ProASIC®3 devices)
      via JTAG (IEEE 1532–compliant)†
   • FlashLock® to Secure FPGA Contents
Low Power
   • Core Voltage for Low Power
   • Support for 1.5 V-Only Systems
   • Low-Impedance Flash Switches
High-Performance Routing Hierarchy
   • Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
   • 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
   • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
   • Wide Range Power Supply Voltage Support per JESD8-B,
      Allowing I/Os to Operate from 2.7 V to 3.6 V
   • Bank-Selectable I/O Voltages—up to 4 Banks per Chip
   • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
      2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
      2.5 V / 5.0 V Input
   • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
      M-LVDS (A3P250 and above)
   • I/O Registers on Input, Output, and Enable Paths
   • Hot-Swappable and Cold Sparing I/Os‡
   • Programmable Output Slew Rate† and Drive Strength
   • Weak Pull-Up/-Down
   • IEEE 1149.1 (JTAG) Boundary Scan Test
   • Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
   • Six CCC Blocks, One with an Integrated PLL
   • Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
      and External Feedback
   • Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
   • 1 kbit of FlashROM User Nonvolatile Memory
   • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
      Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
   • True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
   • M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor
      Available with or without Debug

General Description
ProASIC3, the third-generation Family of Actel Flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® Family. Nonvolatile Flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os

Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off

High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†

In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents

Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches

High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)

ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft Processor Available with or without Debug

[Actel]

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Features and Benefits
High Capacity
   • 15 k to 1 M System Gates
   • Up to 144 kbits of True Dual-Port SRAM
   • Up to 300 User I/Os
Reprogrammable Flash Technology
   • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
      Process
   • Live at Power-Up (LAPU) Level 0 Support
   • Single-Chip Solution
   • Retains Programmed Design when Powered Off
High Performance
   • 350 MHz System Performance
   • 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
   • Secure ISP Using On-Chip 128-Bit Advanced
      Encryption Standard (AES) Decryption (except ARM®-
      enabled ProASIC®3 devices) via JTAG (IEEE 1532–
      compliant)†
   • FlashLock® to Secure FPGA Contents
Low Power
   • Core Voltage for Low Power
   • Support for 1.5 V-Only Systems
   • Low-Impedance Flash Switches
High-Performance Routing Hierarchy
   • Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
   • 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
   • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
   • Bank-Selectable I/O Voltages—up to 4 Banks per Chip
   • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
      2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and
      LVCMOS 2.5 V / 5.0 V Input
   • Differential I/O Standards: LVPECL, LVDS, BLVDS, and
      M-LVDS (A3P250 and above)
   • I/O Registers on Input, Output, and Enable Paths
   • Hot-Swappable and Cold Sparing I/Os‡
   • Programmable Output Slew Rate† and Drive Strength
   • Weak Pull-Up/-Down
   • IEEE 1149.1 (JTAG) Boundary Scan Test
   • Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
   • Six CCC Blocks, One with an Integrated PLL
   • Configurable Phase-Shift, Multiply/Divide, Delay
      Capabilities and External Feedback
   • Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
   • 1 kbit of FlashROM User Nonvolatile Memory
   • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
      RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
   • True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
   • M1 and M7 ProASIC3 Devices—Cortex-M1 and
      CoreMP7 Soft Processor Available with or without
      Debug

Product Highlights

The ARM (Autoranging Rectifier Module) is an AC front end module which provides autoranging line rectification and inrush current limiting. The ARM is available in either 500/750W or 750/1000W models in a

mini sized package measuring only 2.28" x 1.45" x 0.5".

Features

• Autoranging input

• Microprocessor controlled

• VI-ARM-1

  500 Watts @ 90-132Vac

  750 Watts @ 180-264Vac

• VI-ARM-2

  1000 Watts @ 90-132Vac

  1500 Watts @ 180-264Vac

• 96-98% Efficiency

• 100˚C baseplate (no derating)

• UL, CSA, TÜV, VDE, BABT

• AC Bus OK, module enable

• Inrush limiting (no external circuitry)

• CE Marked



Typical Applications: systems requiring a rugged, full featured interface to the AC mains in the smallest possible package.

High Capacity

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os



Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI



In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM®-enabled ProASIC®3 devices)via JTAG (IEEE 1532–compliant)

• FlashLock®to Secure FPGA Contents



Low Power

• Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

 

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure



Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Wide Range Power Supply Voltage Support per JESD8-B,Allowing I/Os to Operate from 2.7 V to 3.6 V

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X

and LVCMOS 2.5 V / 5.0 V Input

• Differential I/O  Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family



Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)



Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)



ARM Processor Support in ProASIC3 FPGAs

• M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor Available with or without Debug

Description

The Atmel SAM4S series is a member of a Family of Flash microcontrollers based on the high

performance 32-bit ARM Cortex-M4 RISC processor. It operates at a maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with Optional dual bank implementation and cache memory, and up to 160 Kbytes of SRAM.

Features

• Core

– ARM®Cortex®-M4 with a 2Kbytes cache running at up to 120 MHz

– Memory Protection Unit (MPU)

– DSP Instruction Set

–Thumb®-2 instruction set

• Pin-to-pin compatible with SAM3N, SAM3S products (64- and 100- pin versions) and SAM7S legacy products (64-pin version)

• Memories

– Up to 2048 Kbytes embedded Flash withOptional dual bank and cache memory

– Up to 160 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded boot loaderroutines (UART, USB) and IAP routines

– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash Support

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector(BOD) and Watchdog for safe operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and Optional low-power 32.768 kHz for RTC or device clock

– RTC with Gregorian and Persian Calendar mode, waveform generation in low power modes

– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– Two PLLs up to 240 MHz for device clock and for USB

– Temperature Sensor

– Up to 22 Peripheral DMA (PDC) Channels

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.



The ARM Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of Support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals.



The ARM Cortex-M3 CPU also includes an internal prefetch unit that Supports speculative branches.

The LPC178x/7x adds a specialized Flash memory accelerator to accomplish optimal performance when executing code from Flash. The LPC178x/7x operates at up to 120 MHz CPU frequency.

FEATURES
• Autoranging Input
• Microprocessor Controlled
• 96-98% Efficiency
• 100°C Baseplate (no derating)
• UL, CSA, TÜV, VDE, BABT, CE Marked, C-Tick
• Bus AC OK, Module Enable
• Inrush Limiting (no external circuitry)
• CE Marked