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Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock® Designed to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC®3E Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz

ARM® Processor Support in ProASIC3E FPGAs

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Features and Benefits
High Capacity
   • 15 k to 1 M System Gates
   • Up to 144 kbits of True Dual-Port SRAM
   • Up to 300 User I/Os
Reprogrammable Flash Technology
   • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
      Process
   • Instant On Level 0 Support
   • Single-Chip Solution
   • Retains Programmed Design when Powered Off
High Performance
   • 350 MHz System Performance
   • 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
   • ISP Using On-Chip 128-Bit Advanced Encryption Standard
      (AES) Decryption (except ARM®-enabled ProASIC®3 devices)
      via JTAG (IEEE 1532–compliant)†
   • FlashLock® to Secure FPGA Contents
Low Power
   • Core Voltage for Low Power
   • Support for 1.5 V-Only Systems
   • Low-Impedance Flash Switches
High-Performance Routing Hierarchy
   • Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
   • 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
   • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
   • Wide Range Power Supply Voltage Support per JESD8-B,
      Allowing I/Os to Operate from 2.7 V to 3.6 V
   • Bank-Selectable I/O Voltages—up to 4 Banks per Chip
   • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
      2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
      2.5 V / 5.0 V Input
   • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
      M-LVDS (A3P250 and above)
   • I/O Registers on Input, Output, and Enable Paths
   • Hot-Swappable and Cold Sparing I/Os‡
   • Programmable Output Slew Rate† and Drive Strength
   • Weak Pull-Up/-Down
   • IEEE 1149.1 (JTAG) Boundary Scan Test
   • Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
   • Six CCC Blocks, One with an Integrated PLL
   • Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
      and External Feedback
   • Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
   • 1 kbit of FlashROM User Nonvolatile Memory
   • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
      Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
   • True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
   • M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor
      Available with or without Debug

[Actel]

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Features and Benefits
High Capacity
   • 15 k to 1 M System Gates
   • Up to 144 kbits of True Dual-Port SRAM
   • Up to 300 User I/Os
Reprogrammable Flash Technology
   • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
      Process
   • Live at Power-Up (LAPU) Level 0 Support
   • Single-Chip Solution
   • Retains Programmed Design when Powered Off
High Performance
   • 350 MHz System Performance
   • 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
   • Secure ISP Using On-Chip 128-Bit Advanced
      Encryption Standard (AES) Decryption (except ARM®-
      enabled ProASIC®3 devices) via JTAG (IEEE 1532–
      compliant)†
   • FlashLock® to Secure FPGA Contents
Low Power
   • Core Voltage for Low Power
   • Support for 1.5 V-Only Systems
   • Low-Impedance Flash Switches
High-Performance Routing Hierarchy
   • Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
   • 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
   • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
   • Bank-Selectable I/O Voltages—up to 4 Banks per Chip
   • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
      2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and
      LVCMOS 2.5 V / 5.0 V Input
   • Differential I/O Standards: LVPECL, LVDS, BLVDS, and
      M-LVDS (A3P250 and above)
   • I/O Registers on Input, Output, and Enable Paths
   • Hot-Swappable and Cold Sparing I/Os‡
   • Programmable Output Slew Rate† and Drive Strength
   • Weak Pull-Up/-Down
   • IEEE 1149.1 (JTAG) Boundary Scan Test
   • Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
   • Six CCC Blocks, One with an Integrated PLL
   • Configurable Phase-Shift, Multiply/Divide, Delay
      Capabilities and External Feedback
   • Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
   • 1 kbit of FlashROM User Nonvolatile Memory
   • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
      RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
   • True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
   • M1 and M7 ProASIC3 Devices—Cortex-M1 and
      CoreMP7 Soft Processor Available with or without
      Debug

High Capacity

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os



Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI



In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM®-enabled ProASIC®3 devices)via JTAG (IEEE 1532–compliant)

• FlashLock®to Secure FPGA Contents



Low Power

• Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

 

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure



Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Wide Range Power Supply Voltage Support per JESD8-B,Allowing I/Os to Operate from 2.7 V to 3.6 V

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X

and LVCMOS 2.5 V / 5.0 V Input

• Differential I/O  Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family



Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)



Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)



ARM Processor Support in ProASIC3 FPGAs

• M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor Available with or without Debug

Description

The Atmel SAM4S series is a member of a Family of Flash microcontrollers based on the high

performance 32-bit ARM Cortex-M4 RISC processor. It operates at a maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with Optional dual bank implementation and cache memory, and up to 160 Kbytes of SRAM.

Features

• Core

– ARM®Cortex®-M4 with a 2Kbytes cache running at up to 120 MHz

– Memory Protection Unit (MPU)

– DSP Instruction Set

–Thumb®-2 instruction set

• Pin-to-pin compatible with SAM3N, SAM3S products (64- and 100- pin versions) and SAM7S legacy products (64-pin version)

• Memories

– Up to 2048 Kbytes embedded Flash withOptional dual bank and cache memory

– Up to 160 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded boot loaderroutines (UART, USB) and IAP routines

– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash Support

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector(BOD) and Watchdog for safe operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and Optional low-power 32.768 kHz for RTC or device clock

– RTC with Gregorian and Persian Calendar mode, waveform generation in low power modes

– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– Two PLLs up to 240 MHz for device clock and for USB

– Temperature Sensor

– Up to 22 Peripheral DMA (PDC) Channels

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.



The ARM Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of Support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals.



The ARM Cortex-M3 CPU also includes an internal prefetch unit that Supports speculative branches.

The LPC178x/7x adds a specialized Flash memory accelerator to accomplish optimal performance when executing code from Flash. The LPC178x/7x operates at up to 120 MHz CPU frequency.

General description
The new Pegoda is NXP’s latest generation of reference designs for secure MIFARE applications. Built around proven, well-established MIFARE solutions and powerful ARM Cortex-M3 processors, these design in kits are available in two evaluation kits: the MFEV710 and the MFEV852.
The MFEV710 design in kit includes the MFRD710 contactless smartcard reader, a design based on the MFRC523 contactless reader IC. The kit Supports the entire MIFARE portfolio: MIFARE Classic, MIFARE DESFire, MIFARE Plus, and MIFARE Ultralight C, including SAM AV2 (in x- and non-x modes). The kits also offer full Support of MIFARE discover, with a reader library for all the MIFARE card products.

Features and benefits
Features
■ Multiprotocol ISO/IEC 14443 and MIFARE operation
■ PC/SC-based architecture on widely deployed hardware solutions
■ Full Support for entire MIFARE card portfolio and MIFAREdiscover
■ SAM Support in standard or x-mode
■ ARM Cortex-M3 microcontroller with integrated Flash memory
■ Firmware in source code and binaries
■ USB host interface to PC and Windows-based user interface
■ Optional Support for RS232, RS485, JTAG, Ethernet

Benefits
■ Fast, flexible development of SAM-based, secure reader systems
■ Quick embedded development with portable code
■ Easy customization with Flash-based microcontroller
■ Custom firmware and JTAG debugging with Optional hardware extension board

Applications
■ Public transportation
■ Access management
■ PC peripheral terminal

 General description

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of Support block integration. The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that Supports speculative branching.

Features and benefits

* ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1768/67/66/65/64/63) or ofup to 120 MHz (LPC1769). A Memory Protection Unit

(MPU) Supporting eight regions is included.

* ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

* Up to 512 kB on-chip Flash programming memory. Enhanced Flash memory accelerator

enables high-speed 120 MHz operation with zero wait states.

* In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader Software.

* On-chip SRAM includes:

* 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU

access.