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ICST
Integrated Circuit Systems
Description : 8-BIT LVDS TRANSMITTER FOR VIDEO

General Description
The V385 transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) Data streams while the transmit clock input is transmitted in parallel with the Data streams over a fifth LVDS link. The V385 can be programmed for Rising Edge or falling Edge clocks through pin R_FB.
ICS manufactures a large variety of video application devices. Consult ICS for all of your video application requirements.

Features
• Pin and function compatible with the National
   DS90C385, TI SN65LVDS93 and THine THC63LVDM83
• Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS streams
• Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth
• Wide clock frequency range from 20 MHz to 85 MHz
• Spread spectrum compatible
• Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Single 3.3 V low-power CMOS design
• Programmable Rising or falling Edge Strobe
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)

ICST
Integrated Circuit Systems
Description : 8-BIT LVDS TRANSMITTER FOR VIDEO

General Description
The V385A transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) Data streams while the transmit clock input is transmitted in parallel with the Data streams over a fifth LVDS link.
Compared to the V385, the V385A provides an extended clock frequency range of 12-90 MHz, rather than 20-85 MHz. Other performance improvements have been incorporated as well.
The V385A can be programmed for Rising Edge or falling Edge clocks through pin R_FB.

Features
• Extended clock frequency range of 12 to 90 MHz
• Pin and function compatible with the National
   DS90C385, TI SN65LVDS93 and THine
   THC63LVDM83, but with extended clock frequency
   and operating temperature range
• Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS streams
• Up to 2.52 Gbps throughput or 315 Megabytes/sec bandwidth
• Spread spectrum compatible
• Supports SD, HD and VGA graphics applications
LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Single 3.3 V low-power CMOS design
• Operating temperature of 0 to +70°C
• Programmable Rising or falling Edge Strobe
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)

Fairchild
Fairchild Semiconductor
Description : Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

Description

The FIN3385 and FIN3386 transform 28-Bit wide parallel Low-Voltage TTL (LVTTL) Data into four serial Low Voltage Differential Signaling (LVDS) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data stream over a separate LVDS link. Every cycle of transmit clock, 28-Bits of input LVTTL Data are sampled and transmitted.

The FIN3386 receives and converts the 4/3 serial LVDS Data streams back into 28/21 bits of LVTTL Data, acting as the deserializer.



Features

Operation -40°C to +85°C

Low Power Consumption

20MHz to 85MHz Shift Clock Support

±1V Common-Mode Range around 1.2V

Narrow Bus Reduces Cable Size and Cost

High Throughput (up to 2.38Gbps)

Internal PLL with No External Component

Compatible with TIA/EIA-644 Specification

56-Lead, TSSOP Package


Description : Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers

General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) Data into 4 serial LVDS (Low Voltage Differential Signaling) Data streams. A phaselocked transmit clock is transmitted in parallel with the Data stream over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL Data are sampled and transmitted.

Features
■ Low power consumption
■ 20 MHz to 85 MHz shift clock support
■ r1V common-mode range around 1.2V
■ Narrow bus reduces cable size and cost
■ High throughput (up to 2.38 Gbps throughput)
■ Internal PLL with no external component
■ Compatible with TIA/EIA-644 specification
■ Devices are offered 56-lead TSSOP packages

Novatek
Novatek Microelectronics
Description : LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface

General Description
The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) Data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable Edge Data Strobes for convenient interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for Rising Edge Strobe(RFB=1) or falling Edge Strobe(RFB=0) through the RFB pin. When transmitting, Data bits D0 - D27 are each loaded into registers of the NT7181 on the Rising Edge or falling Edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the Data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The Data bus appears the same at the input to the transmitting and output of the receiver with the Data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.

Features
■ 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput
■ Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI
■ 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential
■ Operates From a Single 3.3V Supply With 250mW (Typ)
■ Low profile 56 Lead TSSOP Package
■ Clock Edge Programmable for Transmitter
■ Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz
■ Supports Spread Spectrum Clock Generator
■ Suggests to use for LCD monitor only
■ No External Components Required for PLL

ETC
Unspecified
Description : LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface

[NOVATEK]

General Description
The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) Data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable Edge Data Strobes for convenient interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for Rising Edge Strobe(RFB=1) or falling Edge Strobe(RFB=0) through the RFB pin. When transmitting, Data bits D0 - D27 are each loaded into registers of the NT7181 on the Rising Edge or falling Edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the Data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The Data bus appears the same at the input to the transmitting and output of the receiver with the Data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.

Features
■ 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput
■ Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI
■ 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential
■ Operates From a Single 3.3V Supply With 250mW (Typ)
■ Low profile 56 Lead TSSOP Package
■ Clock Edge Programmable for Transmitter
■ Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz
■ Supports Spread Spectrum Clock Generator
■ Suggests to use for LCD monitor only
■ No External Components Required for PLL

Part Name(s) : THC63LVD823
THINE
THine Electronics, Inc.
Description : Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA

General Description
The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.
   
Features
• Wide dot clock range: 25-135MHz suited for VGA,
    SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Dual Link, Dual-in (TTL)/Dual-out
    (LVDS) pixel up to 170MHz dot clock for UXGA
• Supports Single Link, Dual-in (TTL)/Single-out
    (LVDS) pixel up to 135MHz dot clock for SXGA+
• Supports Single Link, Single-in (TTL)/Single-out
    (LVDS) pixel up to 85MHz dot clock for XGA
• Clock Edge selectable
• Supports Reduced swing LVDS for Low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 100pin TQFP
• THC63LVDM83R compatible
   

Description : Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

General Description
The MAX9268 deserializer utilizes Maxim’s gigabit multimedia serial link (GMSL) technology. The MAX9268 deserializer features an LVDS system interface for reduced pin count and a smaller package, and pairs with any GMSL serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and bidirectional control Data.

Features
♦ Pairs with Any GMSL Serializer
♦ 2.5Gbps Payload-Rate AC-Coupled Serial Link
♦ Scrambled 8b/10b Line Coding
♦ Supports WXGA (1280 x 800) with 24-Bit Color
♦ 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz to 78MHz (4-Channel LVDS) Output Clock
♦ 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S Audio Channel Supports High-Definition Audio
♦ Embedded Half-/Full-Duplex Bidirectional Control Channel (100kbps to 1Mbps)
♦ Two 3-Level Inputs Support 9 Device Addresses
♦ Interrupt Supports Touch-Screen Functions for Display Panels
♦ I2C Master for Peripherals
♦ Equalizer for Serial Link Input
♦ Programmable Spread Spectrum on the LVDS and Control Outputs for Reduced EMI
♦ Serial-Data Clock Recovery Eliminates an External Clock
♦ Automatic Data-Rate Detection Allows On-the-Fly Data-Rate Change
♦ Built-In PRBS Generator for BER Testing of the Serial Link
♦ ISO 10605 and IEC 61000-4-2 ESD Protection
♦ -40NC to +105NC Operating Temperature Range
♦ 1.8V to 3.3V I/O and 3.3V Core Supplies
♦ Patent Pending

Applications
    High-Resolution Automotive Navigation
    Rear-Seat Infotainment
    Megapixel Camera Systems

ON-Semiconductor
ON Semiconductor
Description : 3.3V LVDS, 1-Bit, High-Speed Differential Driver

Description
This single driver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350mV, which provides low EMI at ultra-low power dissipation even at high frequencies. This device is ideal for high-speed transfer of clock or Data.
The FIN1017 can be paired with its companion receiver, the FIN1018, or with any other LVDS receiver.

Features
■ Greater than 600Mbs Data Rate
3.3V Power Supply Operation
■ 0.5ns Maximum Differential Pulse Skew
■ 1.5ns Maximum Propagation Delay
■ Low Power Dissipation
■ Power-Off Protection
■ Meets or Exceeds the TIA/EIA-644 LVDS Standard
■ Flow-Through Pinout Simplifies PCB Layout
■ 8-Lead SOIC and US8 Packages Save Space

Fairchild
Fairchild Semiconductor
Description : 3.3V LVDS 2-Bit High Speed Differential Receiver

General Description
This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and Data.
The FIN1028 can be paired with its companion driver, the FIN1027, or any other LVDS driver.

Features
■ Greater than 400Mbs Data rate
3.3V power supply operation
■ 0.4ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Fail safe protection for open-circuit, shorted and
   terminated conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Flow-through pinout simplifies PCB layout

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