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Part Name(s) : DS90CR287_04 DS90CR287MTD_04 DS90CR287MTDX_04 DS90CR288A DS90CR288AMTD DS90CR288AMTDX National-Semiconductor
National ->Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz View

General Description
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL Data into four LVDS (Low Voltage Differential Signal ing) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input Data are sampled and transmitted. The DS90CR288A receiver converts the four LVDS Data streams back into 28 bits of LVCMOS/LVTTL Data. At a transmit clock frequency of 85 MHz, 28 bits of TTL Data are transmitted at a rate of 595 Mbps per LVDS Data Channel. Using a 85 MHz clock, the Data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

Features
■ 20 to 85 MHz shift clock support
■ 50% duty cycle on receiver output clock
■ 2.5 / 0 ns Set & Hold Times on TxINPUTs
■ Low power consumption
■ ±1V common-mode range (around +1.2V)
■ Narrow bus reduces cable size and cost
■ Up to 2.38 Gbps throughput
■ Up to 297.5 Mbytes/sec bandwidth
■ 345 mV (typ) swing LVDS devices for low EMI
■ PLL requires no external components
Rising Edge Data Strobe
■ Compatible with TIA/EIA-644 LVDS standard
■ Low profile 56-lead TSSOP package

Part Name(s) : DS90CR285 DS90CR285MTD DS90CR285MTDX DS90CR286 DS90CR286MTD DS90CR286MTDX National-Semiconductor
National ->Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz View

General Description

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL Data into four LVDS (Low Voltage Differential Signal ing) Data streams. A phase-locked transmit clock is transmit ted in parallel with the Data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input Data are sampled and transmitted. The DS90CR286 receiver converts the LVDS Data streams back into 28 bits of LVCMOS/LVTTL Data. At a transmit clock frequency of 66 MHz, 28 bits of TTL Data are transmitted at a rate of 462 Mbps per LVDS Data Channel. Using a 66 MHz clock, the Data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the Data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-Bit wide Data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 Data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables’ smaller form factor.



Features

■ Single +3.3V supply

■ Chipset (Tx + Rx) power consumption <250 mW (typ)

■ Power-down mode (<0.5 mW total)

■ Up to 231 Megabytes/sec bandwidth

■ Up to 1.848 Gbps Data throughput

■ Narrow bus reduces cable size

■ 290 mV swing LVDS devices for low EMI

■ +1V common mode range (around +1.2V)

■ PLL requires no external components

■ Both devices are offered in a Low profile 56-lead TSSOP package

Rising Edge Data Strobe

■ Compatible with TIA/EIA-644 LVDS standard

■ ESD Rating > 7 kV

■ Operating Temperature: −40˚C to +85˚C



 


Part Name(s) : DS90CR217 DS90CR217MTD DS90CR217MTDX National-Semiconductor
National ->Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz View

General Description

The DS90CR217 transmitter converts 21 bits of CMOS/TTL Data into three LVDS (Low Voltage Differential Signaling) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input Data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL Data are transmitted at a rate of 595 Mbps per LVDS Data Channel. Using a 85 MHz clock, the Data through put is 1.785 Gbit/s (223 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.



Features

■ 20 to 85 MHz shift clock support

■ 50% duty cycle on receiver output clock

■ Best-in-Class Set & Hold Times on TxINPUTs

■ Low power consumption

■ ±1V common-mode range (around +1.2V)

■ Narrow bus reduces cable size and cost

■ Up to 1.785 Gbps throughput

■ Up to 223 Mbytes/sec bandwidth

■ 345 mV (typ) swing LVDS devices for low EMI

■ PLL requires no external components

Rising Edge Data Strobe

■ Compatible with TIA/EIA-644 LVDS standard

■ Low profile 48-lead TSSOP package



 


Part Name(s) : DS90CR218A DS90CR218AMTD DS90CR218AMTDX National-Semiconductor
National ->Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz View

General Description

The DS90CR218A receiver deserializes three input LVDS Data streams into 21 bits of CMOS/TTL output Data. When operating at the maximum input clock rate of 85 MHz, the LVDS Data is received at 595 Mbps per Data Channel for a total Data throughput of 1.785 Gbit/sec (233 Mbytes/sec). The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.



Features

■ 12 to 85 MHz shift clock support

■ 50% duty cycle on receiver output clock

■ Low power consumption

■ ±1V common-mode range (around +1.2V)

■ Narrow bus reduces cable size and cost

■ Up to 1.785 Gbps throughput

■ Up to 223 Mbytes/sec bandwidth

■ 345 mV (typ) swing LVDS devices for low EMI

■ PLL requires no external components

Rising Edge Data Strobe

■ Compatible with TIA/EIA-644 LVDS standard

■ Low profile 48-lead TSSOP package



 



Part Name(s) : DS90CR218 DS90CR218MTD DS90CR218MTDX National-Semiconductor
National ->Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz View

General Description

The DS90CR217 transmitter converts 21 bits of CMOS/TTL Data into three LVDS (Low Voltage Differential Signaling) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input Data are sampled and transmitted. The DS90CR218 receiver converts the three LVDS Data streams back into 21 bits of CMOS/TTL Data. At a transmit clock frequency of 75 MHz, 21 bits of TTL Data are transmitted at a rate of 525 Mbps per LVDS Data Channel. Using a 75 MHz clock, the Data throughput is 1.575 Gbit/s (197 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.



Features

■ 20 to 75 MHz shift clock support

■ 50% duty cycle on receiver output clock

■ Best–in–Class Set & Hold Times on TxINPUTs and RxOUTPUTs

■ Low power consumption

■ Tx + Rx Power-down mode <400µW (max)

■ ±1V common mode range (around +1.2V)

■ Narrow bus reduces cable size and cost

■ Up to 1.575 Gbps throughput

■ Up to 197 Megabytes/sec bandwidth

■ 345 mV (typ) swing LVDS devices for low EMI

■ PLL requires no external components

Rising Edge Data Strobe

■ Compatible with TIA/EIA-644 LVDS standard

■ Low profile 48-lead TSSOP package



 


Part Name(s) : DS90CR285 DS90CR285MTD DS90CR285MTD/NOPB DS90CR285MTDX DS90CR285MTDX/NOPB DS90CR286 DS90CR286MTD DS90CR286MTD/NOPB DS90CR286MTDX DS90CR286MTDX/NOPB Texas-Instruments
Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz View

DESCRIPTION

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL Data into four LVDS (Low Voltage Differential Signaling) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input Data are sampled and transmitted. The DS90CR286 receiver converts the LVDS Data streams back into 28 bits of LVCMOS/LVTTL Data. At a transmit clock frequency of 66 MHz, 28 bits of TTL Data are transmitted at a rate of 462 Mbps per LVDS Data Channel. Using a 66 MHz clock, the Data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the Data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-Bit wide Data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 Data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.



FEATURES

• Single +3.3V Supply

• Chipset (Tx + Rx) Power Consumption <250 mW (typ)

• Power-Down Mode (<0.5 mW total)

• Up to 231 Megabytes/sec Bandwidth

• Up to 1.848 Gbps Data Throughput

• Narrow Bus Reduces Cable Size

• 290 mV Swing LVDS Devices for Low EMI

• +1V Common Mode Range (Around +1.2V)

• PLL Requires no External Components

• Both Devices are Offered in a Low Profile 56-Lead TSSOP Package

Rising Edge Data Strobe

• Compatible with TIA/EIA-644 LVDS Standard

• ESD Rating > 7 kV

• Operating Temperature: −40°C to +85°C



 


Part Name(s) : DS90CR287 DS90CR287MTD DS90CR287MTD/NOPB DS90CR287MTDX/NOPB DS90CR287SLC/NOPB DS90CR288A DS90CR288AMTD DS90CR288AMTD/NOPB DS90CR288AMTDX DS90CR288AMTDX/NOPB Texas-Instruments
Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz View

DESCRIPTION
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL Data into four LVDS (Low Voltage Differential Signaling) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input Data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS Data streams back into 28 bits of LVCMOS/LVTTL Data. At a transmit clock frequency of 85 MHz, 28 bits of TTL Data are transmitted at a rate of 595 Mbps per LVDS Data Channel. Using a 85 MHz clock, the Data
throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

FEATURES
• 20 to 85 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• 2.5 / 0 ns Set & Hold Times on TxINPUTs
• Low Power Consumption
• ±1V Common-Mode Range (around +1.2V)
• Narrow Bus Reduces Cable Size and Cost
• Up to 2.38 Gbps Throughput
• Up to 297.5 Mbytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires no External Components
Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 56-Lead TSSOP Package

Part Name(s) : DS90CR287 DS90CR288A DS90CR287MTD DS90CR287MTD/NOPB DS90CR287MTDX/NOPB DS90CR287SLC/NOPB DS90CR288AMTD DS90CR288AMTD/NOPB DS90CR288AMTDX DS90CR288AMTDX/NOPB TI
Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz View

DESCRIPTION
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL Data into four LVDS (Low Voltage Differential Signaling) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input Data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS Data streams back into 28 bits of LVCMOS/LVTTL Data. At a transmit clock frequency of 85 MHz, 28 bits of TTL Data are transmitted at a rate of 595 Mbps per LVDS Data Channel. Using a 85 MHz clock, the Data
throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

FEATURES
• 20 to 85 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• 2.5 / 0 ns Set & Hold Times on TxINPUTs
• Low Power Consumption
• ±1V Common-Mode Range (around +1.2V)
• Narrow Bus Reduces Cable Size and Cost
• Up to 2.38 Gbps Throughput
• Up to 297.5 Mbytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires no External Components
Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 56-Lead TSSOP Package

Part Name(s) : DS90CR216A DS90CR216AMTD DS90CR286A DS90CR286AMTD National-Semiconductor
National ->Texas Instruments
Description : +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit View

The DS90CR286A receiver converts the four LVDS Data streams (Up to 1.848 Gbps throughput or 231 Megabytes/ sec bandwidth) back into parallel 28 bits of CMOS/TTL Data.



Also available is the DS90CR216A that converts the three LVDS Data streams (Up to 1.386 Gbps throughput or 173 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL Data. Both Receivers’ outputs are Rising Edge Strobe.


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