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Part Name(s) : MCM63P736 MCM63P818 MCM63P736TQ133 MCM63P736TQ100 MCM63P736TQ66 MCM63P736TQ133R MCM63P736TQ100R MCM63P736TQ66R MCM63P736ZP133 MCM63P736ZP100 Motorola
Motorola => Freescale
Description : 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM View

The MCM63P736 and MCM63P818 are 4M Bit Synchronous Fast Static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 Bits each and the MCM63P818 is organized as 256K words of 18 Bits each. These devices integrate input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
    MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)
    MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Two–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

Part Name(s) : MCM63Z736 MCM63Z818 MCM63Z736TQ133 MCM63Z736TQ100 MCM63Z736TQ133R MCM63Z736TQ100R MCM63Z818TQ133 MCM63Z818TQ100 MCM63Z818TQ133R MCM63Z818TQ100R Motorola
Motorola => Freescale
Description : 128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM View

The ZBT RAM is a 4M–Bit Synchronous Fast Static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 Bits each and the MCM63Z818 is organized as 256K words of 18 Bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
    MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Two–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package

Part Name(s) : MCM69P818 MCM69P818ZP3.5 MCM69P818ZP3.8 MCM69P818ZP4 MCM69P818ZP3.5R MCM69P818ZP3.8R MCM69P818ZP4R Motorola
Motorola => Freescale
Description : 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM View

The MCM69P818 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 256K words of 18 Bits each. This device integrates input registers, an output register, a 2–Bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69P818–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
    MCM69P818–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
    MCM69P818–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• 2–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Part Name(s) : MCM63Z737 MCM63Z819 MCM63Z737TQ11 MCM63Z737TQ15 MCM63Z737TQ11R MCM63Z737TQ15R MCM63Z819TQ11 MCM63Z819TQ15 MCM63Z819TQ11R MCM63Z819TQ15R Motorola
Motorola => Freescale
Description : 128K x 36 and 256K x 18 Bit Flow–Through ZBT™ RAM Synchronous Fast Static RAM View

The ZBT RAM is a 4M–Bit Synchronous Fast Static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z737 is organized as 128K words of 36 Bits each and the MCM63Z819 is organized as 256K words of 18 Bits each, fabricated with high performance silicon gate CMOS technology.

• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z737/MCM63Z819–11 = 11 ns Access/15 ns Cycle (66 MHz)
    MCM63Z737/MCM63Z819–15 = 15 ns Access/20 ns Cycle (50 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Single–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package


Part Name(s) : A67L8316E-45 A67L8316E-6 AMICC
AMIC Technology
Description : 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM View

General Description
The AMIC Direct Bus Alternation™ (DBA™ ) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8316, A67L8318, A67L7332, A67L7336 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced Synchronous peripheral circuitry and a 2-Bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write Read alternation. The positive edge triggered single clock input (CLK) controls all Synchronous inputs passing through the registers.

Features
Fast access time: 4.0/4.2/4.5/5.0 ns (143,133,117,100MHz)
● Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization
● Signal +3.3V ±5% power supply
● Individual Byte Write control capability
● Clock enable (CEN) pin to enable clock and suspend operations
● Clock-controlled and registered address, data and control signals
● Registered output for Pipelined applications
● Three separate chip enables allow wide range of options for CE control, address pipelining
● Internally self-timed write cycle
● Selectable BURST mode (Linear or Interleaved)
● SLEEP mode (ZZ pin) provided
● Available in 100 pin LQFP package

Part Name(s) : MCM67J518FN6 MCM67J518FN7 MCM67J518FN9 MCM67J518 Motorola
Motorola => Freescale
Description : 32K x 18 Bit BurstRAMSynchronous Fast Static RAM View

32K x 18 Bit BurstRAMSynchronous Fast Static RAM With Burst Counter and Registered Outputs

The MCM67J518 is a 589,824 Bit Synchronous Static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium microprocessors. It is organized as 32,768 words of 18 Bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–Bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz, 9 ns/66 MHz
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Output Registers for Pipelined Applications
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• ASynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
• ADSP Disabled with Chip Enable (E) – Supports Address Pipelining

Part Name(s) : MCM69F735 MCM69F735ZP6 MCM69F735ZP6.5 MCM69F735ZP7 MCM69F735ZP6R MCM69F735ZP6.5R MCM69F735ZP7R Motorola
Motorola => Freescale
Description : 128K x 36 Bit Flow–Through BurstRAMSynchronous Fast Static RAM View

The MCM69F735 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 36 Bits each. This device integrates input registers, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69F735 Speed Options
• 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Part Name(s) : MCM69L817 MCM69L817ZP6 MCM69L817ZP6.5 MCM69L817ZP7 MCM69L817ZP6R MCM69L817ZP6.5R MCM69L817ZP7R Motorola
Motorola => Freescale
Description : 256K x 18 Bit Data Latch BurstRAMSynchronous Fast Static RAM View

The MCM69L817 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 Bits each. This device integrates input registers, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69L817 Speed Options
• 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Part Name(s) : MCM63P733A MCM63P733ATQ177 MCM63P733ATQ177R MCM63P733ATQ133 MCM63P733ATQ117 MCM63P733ATQ100 MCM63P733ATQ90 MCM63P733ATQ133R MCM63P733ATQ117R MCM63P733ATQ100R Motorola
Motorola => Freescale
Description : 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM View

The MCM63P733A is a 4M–Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 32 Bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

The MCM63P733A operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
    MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz)
    MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz)
    MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz)
• 3.3 V + 10%/– 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Single–Cycle Deselect
• Sleep Mode (ZZ)
• 100–Pin TQFP Package

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