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Description : 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM63P737K and MCM63P819K are 4M–Bit Synchronous Fast Static RAMs designed to provide a burstable, high performance, secondary cache. The MCM63P737K (organized as 128K words by 36 Bits) and the MCM63P819K (organized as 256K words by 18 Bits) integrate input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
The MCM63P737K and MCM63P819K operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM63P737K/MCM63P819K–166 = 3.5 ns Access/6 ns Cycle (166 MHz)
   MCM63P737K/MCM63P819K–150 = 3.8 ns Access/6.7 ns Cycle (150 MHz)
   MCM63P737K/MCM63P819K–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V +10%, –5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages

Motorola
Motorola => Freescale
Description : 128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM69P736 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 128K words of 36 Bits each. This device integrates input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
The MCM69P736 operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM69P736–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Two–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Description : 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM69P819 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 256K words of 18 Bits each. This device integrates input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
The MCM69P819 operates from a 3.3 V core power supply and all outputs operate on a 2.5 or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM69P819–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
   MCM69P819–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
   MCM69P819–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

Description : 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM63P736 and MCM63P818 are 4M Bit Synchronous Fast Static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 Bits each and the MCM63P818 is organized as 256K words of 18 Bits each. These devices integrate input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
    MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)
    MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Two–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

Description : 128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM

The ZBT RAM is a 4M–Bit Synchronous Fast Static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 Bits each and the MCM63Z818 is organized as 256K words of 18 Bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
    MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Two–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package

Description : 128K x 36 Bit Data Latch BurstRAMSynchronous Fast Static RAM

128K x 36 Bit Data Latch BurstRAMSynchronous Fast Static RAM

The MCM69L735 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 36 Bits each. This device integrates input registers, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
The MCM69L735 operates from a 3.3 V core power supply and all outputs operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM69L735 Speed Options
• 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Description : 128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM69P737 is a 4M Bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 128K words of 36 Bits each. This device integrates input registers, an output register, a 2–Bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
The MCM69P737 operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM69P737–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
   MCM69P737–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
   MCM69P737–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

Description : 64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM63P636 is a 2M–Bit Synchronous Fast Static RAM designed to provide burstable, high performance, secondary cache for advanced microprocessors. It is organized as 64K words of 36 Bits each. This device integrates input registers, an output register, a 2–Bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows for precise cycle control with the use of an external clock (K) and external strobe clock (SK).
The MCM63P636 operates from a 3.3 V core power supply, a 2.0 V input power supply, and a 2.0 V I/O power supply. These power supplies are designed so that power sequencing is not required.

• MCM63P636–250 = 3.9 ns Access/4 ns Cycle (250 MHz)
  MCM63P636–225 = 4.3 ns Access/4.4 ns Cycle (225 MHz)
  MCM63P636–200 = 4.9 ns Access/5 ns Cycle (200 MHz)
• 3.3 V ± 200 mV VDD Supply, 2.0 V VDDI and VDDQ Supply
• Internally Self–Timed Late Write Cycle
• Three–Cycle Single–Read Latency
• Strobe Clock Input and Data Strobe Output Pins
• On–Chip Output Enable Control
• On–Chip Burst Advance Control
• Four–Tick Burst
• Power–On Reset Pin
• Low Power Stop Clock Operation
• Boundary Scan (PBGA Only)
• JEDEC Standard 153–Pin PBGA and 100–Pin TQFP Packages

Description : 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output

General Description
The A65H73361 and A65H83181 are 128K words by 36 Bits and 256K words by 18 Bits late write Synchronous 4Mb SRAMS built using high performance CMOS process.

Features
Fast access times: 2.5/3.0/3.5ns
128K x 36 or 256K x 18 organizations
■ CMOS technology
■ Register to register Synchronous operation with self-timed late write
■ Single +3.3V ±5% power supply
■ Individual byte write and global write
■ HSTL input & output levels
■ Boundary scan(JTAG) IEEE 1149.1 compatible
■ ASynchronous output enable
■ Sleep mode (ZZ)
■ Programmable impedance output drivers
■ JEDEC Standard pinout and boundary scan order
■ 7 x 17 bump plastic ball grid array (PBGA) package

Description : 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output

General Description
The A65H73361 and A65H83181 are 128K words by 36 Bits and 256K words by 18 Bits late write Synchronous 4Mb SRAMS built using high performance CMOS process.

Features
Fast access times: 2.5/3.0/3.5ns
128K x 36 or 256K x 18 organizations
■ CMOS technology
■ Register to register Synchronous operation with self-timed late write
■ Single +3.3V ±5% power supply
■ Individual byte write and global write
■ HSTL input & output levels
■ Boundary scan(JTAG) IEEE 1149.1 compatible
■ ASynchronous output enable
■ Sleep mode (ZZ)
■ Programmable impedance output drivers
■ JEDEC Standard pinout and boundary scan order
■ 7 x 17 bump plastic ball grid array (PBGA) package

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