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Part Name(s) : NT5DS4M32EG NT5DS4M32EG-5G NT5DS4M32EG-5 NT5DS4M32EG-6 NANOAMP
NanoAmp Solutions, Inc.
Description : 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL View

General Overview
The NT5DS4M32EG is 134,217,728 Bits of Double Data Rate Synchronous dynamic RAM organized as 4 x 1,048,576 Bits by 32 I/Os. Synchronous features With Data Strobe allow extremely high performance up to 400Mbps/pin. I/O transactions are possible on both edges of the clock. Range of operating frequencies, progRAMmable burst length and progRAMmable latencies allow the device to be useful for a variety of high performance memory system applications.

Features
• VDD = 2.5V±5% , VDDQ = 2.5V±5%
• SSTL_2 compatible inputs/outputs
• 4 Banks operation
• MRS cycle With address key progRAMs
    -CAS latency 2,3 (clock)
    -Burst length (2, 4, 8 and Full page)
    -Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except Data & DM are sampled at the rising edge of the system clock
• Differential clock input(CK & /CK)
Data I/O transaction on both edges of Data strobe
• 4 DQS (1 DQS/Byte)
• DLL aligns DQ and DQS transaction With Clock transaction
• Edge aligned Data & Data strobe output
• Center aligned Data & Data strobe input
• DM for write masking only
• Auto & self refresh
32ms refresh period (4K cycle)
• 144-Ball FBGA package
• Maximum clock frequency up to 200MHz
• Maximum Data Rate up to 400Mbps/pin

Part Name(s) : K4D263238M K4D263238M-QC45 K4D263238M-QC50 K4D263238M-QC55 K4D263238M-QC60 Samsung
Samsung
Description : 1M x 32Bit x 4 Banks With Bi-Directional Data Strobe and DLL Double Data Rate Synchronous RAM View

GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238 is 134,217,728 Bits of hyper Synchronous Data Rate Dynamic RAM organized as 4 x 1,048,576 words by 32 Bits, fabricated With SAMSUNG¢s high performance CMOS technology. Synchronous features With Data Strobe allow extremely high performance up to 1.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, progRAMmable burst length and progRAMmable latencies allow the device to be useful for a variety of high performance memory system applications.

FEATURES
• 2.5V ± 5% power supply
• SSTL_2 compatible inputs/outputs
• 4 Banks operation
• MRS cycle With address key progRAMs
    -. Read latency 3,4 (clock)
    -. Burst length (2, 4, 8 and Full page)
    -. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except Data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Write Interrupted by Read function
Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions With Clock transition
• Edge aligned Data & Data strobe output
• Center aligned Data & Data strobe input
• DM for write masking only
• Auto & Self refresh
32ms refresh period (4K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 222MHz
• Maximum Data Rate up to 444Mbps/pin

Part Name(s) : K4D26323RA-GC K4D26323RA-GC2A K4D26323RA-GC33 K4D26323RA-GC36 Samsung
Samsung
Description : 1M x 32Bit x 4 Banks With Bi-Directional Data Strobe and DLL Double Data Rate Synchronous RAM (144-Ball FBGA) View

GENERAL DESCRIPTION

FOR 1M x 32Bit x 4 Bank DDR SDRAM

The K4D26323RA is 134,217,728 Bits of hyper Synchronous Data Rate Dynamic RAM organized as 4 x1,048,576 words by 32 Bits, fabricated With SAMSUNG’s high performance CMOS technology. Synchronous features With Data Strobe allow extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, progRAMmable burst length and progRAMmable latencies allow the device to be useful for a variety of high performance memory system applications.



FEATURES

• 2.8V + 5% power supply for device operation

• 2.8V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 Banks operation

• MRS cycle With address key progRAMs

   -. Read latency 3,4 (clock)

   -. Burst length (2, 4, 8 and Full page)

   -. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except Data & DM are sampled at the positive going edge of the system clock

• Differential clock input

• No Wrtie-Interrupted by Read Function

• 4 DQS’s ( 1DQS / Byte )

Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions With Clock transition

• Edge aligned Data & Data strobe output

• Center aligned Data & Data strobe input

• DM for write masking only

• Auto & Self refresh

32ms refresh period (4K cycle)

• 144-Ball FBGA

• Maximum clock frequency up to 350MHz

• Maximum Data Rate up to 700Mbps/pin



 


Part Name(s) : K4D263238D K4D263238D-QC40 K4D263238D-QC50 Samsung
Samsung
Description : 1M x 32Bit x 4 Banks With Bi-Directional Data Strobe and DLL Double Data Rate Synchronous DRAM View

GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238D is 134,217,728 Bits of hyper Synchronous Data Rate Dynamic RAM organized as 4 x 1,048,576 words by 32 Bits, fabricated With SAMSUNG′s high performance CMOS technology. Synchronous features With Data Strobe allow extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, progRAMmable burst length and progRAMmable latencies allow the device to be useful for a variety of high performance memory system applications.

FEATURES
• 2.5V ± 5% power supply
• SSTL_2 compatible inputs/outputs
• 4 Banks operation
• MRS cycle With address key progRAMs
    -. Read latency 3,4 (clock)
    -. Burst length (2, 4, 8 and Full page)
    -. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except Data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Write Interrupted by Read function
Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions With Clock transition
• Edge aligned Data & Data strobe output
• Center aligned Data & Data strobe input
• DM for write masking only
• Auto & Self refresh
32ms refresh period (4K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 250MHz
• Maximum Data Rate up to 500Mbps/pin


Part Name(s) : K4D263238E-GC K4D263238E-GC25 K4D263238E-GC2A K4D263238E-GC33 K4D263238E-GC36 K4D263238E-GC40 K4D263238E-GC45 Samsung
Samsung
Description : 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM With Bi-Directional Data Strobe and DLL View

GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238E is 134,217,728 Bits of hyper Synchronous Data Rate Dynamic RAM organized as 4 x1,048,576 words by 32 Bits, fabricated With SAMSUNG’s high performance CMOS technology. Synchronous features With Data Strobe allow extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, progRAMmable burst length and progRAMmable latencies allow the device to be useful for a variety of high performance memory system applications.

FEATURES
• VDD/VDDQ = 2.8V ± 5% for -GC25
• VDD/VDDQ = 2.5V ± 5% for -GC2A/33/36/40/45
• SSTL_2 compatible inputs/outputs
• 4 Banks operation
• MRS cycle With address key progRAMs
   -. Read latency 3, 4, 5 (clock)
   -. Burst length (2, 4, 8 and Full page)
   -. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except Data & DM are sampled at the positive
   going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions With Clock transition
• Edge aligned Data & Data strobe output
• Center aligned Data & Data strobe input
• DM for write masking only
• Auto & Self refresh
32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 400MHz
• Maximum Data Rate up to 800Mbps/pin

Part Name(s) : ADD8616A8A ADD8616A8A-75BA VDD8608A8A-75BA ADD8616A8A-75B A-Data
A-Data Technology
Description : Double Data Rate SDRAM 4M x 16 Bit x 4 Banks View

General Description
The ADD8616A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 4,194,304 words x 16 Bits x 4 Banks, Synchronous design allows precise cycle control With the use of system clock I/O transactions are possible on every clock cycle.   
Data outputs occur at both rising edges of CK and /CK.
Range of operating frequencies, progRAMmable burst length and progRAMmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications
   
Features
• 2.5V for VDDQ power supply
• SSTL_2 interface
• MRS Cycle With address key progRAMs
    -CAS Latency (2, 2.5)
    -Burst Length (2,4 &8)
    -Burst Type (sequential & Interleave)
• 4 Banks operation
• Differential clock input (CK, /CK) operation
Double data Rate interface
• Auto & Self refresh
• 8192 refresh cycle
• DQM for masking
• Package:66-pins 400 mil TSOP-Type II
   

Part Name(s) : M13S64164A M13S64164A-5BIG M13S64164A-5TIG M13S64164A-6BIG M13S64164A-6TIG ESMT
[Elite Semiconductor Memory Technology Inc.
Description : 1M x 16 Bit x 4 Banks Double Data Rate SDRAM View

Features

• JEDEC Standard

• Internal pipelined Double-Data-Rate architecture, two Data access per clock cycle

Bi-Directional Data strobe (DQS)

• On-chip DLL

• Differential clock inputs (CLK and CLK )

• DLL aligns DQ and DQS transition With CLK transition

• Quad bank operation

• CAS Latency : 2, 2.5, 3

• Burst Type : Sequential and Interleave

• Burst Length : 2, 4, 8

• All inputs except Data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of Data strobe (DQS)

• DQS is edge-aligned With Data for reads; center-aligned With Data for WRITE

Data mask (DM) for write masking only

• For 2.5V parts, VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V

• Auto & Self refresh

• 64ms refresh period, 4K cycle

• SSTL-2 I/O interface

• 66pin TSOPII and 60 ball BGA package



 


Part Name(s) : 42S32200 IS42S32200 IS42S32200-6TI IS42S32200-7TI IS42S32200-6T IS42S32200-7T ISSI
Integrated Silicon Solution
Description : 512K Bits x 32 Bits x 4 Banks (64-MBIT) Synchronous DYNAMIC RAM View

OVERVIEW
ISSIs 64Mb Synchronous DRAM IS42S32200 is organized as 524,288 Bits x 32-bit x 4-bank for improved performance. The Synchronous DRAMs achieve high-speed Data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to opeRate in 3.3V memory systems containing 67,108,864 Bits. Internally configured as a quad-bank DRAM With a Synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 Bits.

FEATURES
• Clock frequency: 166, 143 MHz
• Fully Synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• ProgRAMmable burst length – (1, 2, 4, 8, full page)
• ProgRAMmable burst sequence: Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• ProgRAMmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Industrial temperature availability
• Package 400-mil 86-pin TSOP II

Part Name(s) : IS42S32200A IS42S32200A-5T IS42S32200A-6T IS42S32200A-7T IS42S32200A-5TI IS42S32200A-6TI IS42S32200A-7TI ISSI
Integrated Silicon Solution
Description : 512K Bits x 32 Bits x 4 Banks (64-MBIT) Synchronous DYNAMIC RAM View

OVERVIEW
ISSIs 64Mb Synchronous DRAM IS42S32200A is organized as 524,288 Bits x 32-bit x 4-bank for improved performance.The Synchronous DRAMs achieve high-speed Data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to opeRate in 3.3V memory systems containing 67,108,864 Bits. Internally configured as a quad-bank DRAM With a Synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 Bits.

FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully Synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• ProgRAMmable burst length – (1, 2, 4, 8, full page)
• ProgRAMmable burst sequence: Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• ProgRAMmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Industrial temperature availability
• Package 400-mil 86-pin TSOP II

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