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Part Name(s) : LH[128KX8/64KX16][128KX8/64KX16]F[128KX8/64KX16][128KX8/64KX16]0BJHE-TTL90 LHF[128KX8/64KX16][128KX8/64KX16]J0[128KX8/64KX16] Sharp
Sharp Electronics
Description : FLASH MEMORY [128Kx8/64Kx16][128Kx8/64Kx16]M ([128Kx8/64Kx16]M × [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]M × [128Kx8/64Kx16]) View

FLASH MEMORY [128Kx8/64Kx16][128Kx8/64Kx16]M ([128Kx8/64Kx16]M × [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]M × [128Kx8/64Kx16])<[128Kx8/64Kx16]p>

Part Name(s) : M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00B M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BMC-[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BMC-55 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BMC-70 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BMC-90 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BTA-[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BTA-90 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BTC-[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BTC-55 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00BTC-70 Macronix
Macronix International
Description : [128Kx8/64Kx16]M-BIT<[128Kx8/64Kx16]font> [[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]] CMOS FLASH MEMORY View

GENERAL DESCRIPTION
The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16]00T[128Kx8/64Kx16]B is a [128Kx8/64Kx16]-mega bit FLASH MEMORY organized as [128Kx8/64Kx16]3[128Kx8/64Kx16],07[128Kx8/64Kx16] bytes or [128Kx8/64Kx16]5,53[128Kx8/64Kx16] words. M[128Kx8/64Kx16]ICs FLASH memories offer the most cost-effective and reliable read[128Kx8/64Kx16]write non-volatile random access MEMORY. The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16]00T[128Kx8/64Kx16]B is pac[128Kx8/64Kx16]aged in [128Kx8/64Kx16][128Kx8/64Kx16]-pin SOP and [128Kx8/64Kx16][128Kx8/64Kx16]-pin TSOP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers.<[128Kx8/64Kx16]p>

FEATURES
• 5V±[128Kx8/64Kx16]0% for read, erase and write operation
[128Kx8/64Kx16]3[128Kx8/64Kx16]07[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16] [128Kx8/64Kx16]553[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16] switchable
• Fast access time:55[128Kx8/64Kx16]70[128Kx8/64Kx16]90[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]0ns
• Low power consumption
    - [128Kx8/64Kx16]0mA ma[128Kx8/64Kx16]imum active current(5MHz)
    - [128Kx8/64Kx16]uA typical standby current
• Command register architecture
    - Byte[128Kx8/64Kx16] Word Programming (7us[128Kx8/64Kx16] [128Kx8/64Kx16][128Kx8/64Kx16]us typical)
    - Erase ([128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-Byte[128Kx8/64Kx16][128Kx8/64Kx16], [128Kx8/64Kx16][128Kx8/64Kx16]-Byte[128Kx8/64Kx16][128Kx8/64Kx16], 3[128Kx8/64Kx16][128Kx8/64Kx16]-Byte[128Kx8/64Kx16][128Kx8/64Kx16], and [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-Byte [128Kx8/64Kx16][128Kx8/64Kx16])
• Auto Erase (chip) and Auto Program
    - Automatically erase any combination of sectors or with Erase Suspend capability.
    - Automatically program and verify data at specified address
• Status Reply
    - Data polling & Toggle bit for detection of program and erase cycle completion.
• Compatibility with JEDEC standard
    - Pinout and software compatible with single-power supply FLASH
    - Superior inadvertent write protection
• Sector protection
    - Hardware method to disable any combination of sectors from program or erase operations
    - Sector protect[128Kx8/64Kx16]unprotect for 5V only system or 5V[128Kx8/64Kx16] [128Kx8/64Kx16][128Kx8/64Kx16]V system
[128Kx8/64Kx16]00,000 minimum erase[128Kx8/64Kx16]program cycles
• Latch-up protected to [128Kx8/64Kx16]00mA from -[128Kx8/64Kx16] to VCC+[128Kx8/64Kx16]V
• Boot Code Sector Architecture
    - T = Top Boot Sector
    - B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.[128Kx8/64Kx16]V
• Pac[128Kx8/64Kx16]age type:
    - [128Kx8/64Kx16][128Kx8/64Kx16]-pin SOP
    - [128Kx8/64Kx16][128Kx8/64Kx16]-pin TSOP
• Ready[128Kx8/64Kx16]Busy pin(RY[128Kx8/64Kx16]BY)
    - Provides a hardware method or detecting program or erase cycle completion
• Erase suspend[128Kx8/64Kx16] Erase Resume
    - Suspend an erase operation to read data from, or program data to a sector that is not being erased, then resume the erase operation.
• Hardware RESET pin
    - Hardware method of resetting the device to reading the device to reading array data.
[128Kx8/64Kx16]0 years data retention<[128Kx8/64Kx16]p>

Part Name(s) : M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00B M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00T M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TMC-[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TMC-55 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TMC-70 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TMC-90 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TTA-[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TTA-90 M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TTC-[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16]00TTC-55 MCNIX
Macronix International
Description : [128Kx8/64Kx16]M-BIT<[128Kx8/64Kx16]font> [[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]] CMOS FLASH MEMORY View

GENERAL DESCRIPTION
The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16]00T[128Kx8/64Kx16]B is a [128Kx8/64Kx16]-mega bit FLASH MEMORY organized as [128Kx8/64Kx16]3[128Kx8/64Kx16],07[128Kx8/64Kx16] bytes or [128Kx8/64Kx16]5,53[128Kx8/64Kx16] words. M[128Kx8/64Kx16]ICs FLASH memories offer the most cost-effective and reliable read[128Kx8/64Kx16]write non-volatile random access MEMORY. The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16]00T[128Kx8/64Kx16]B is pac[128Kx8/64Kx16]aged in [128Kx8/64Kx16][128Kx8/64Kx16]-pin SOP and [128Kx8/64Kx16][128Kx8/64Kx16]-pin TSOP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers.<[128Kx8/64Kx16]p>

FEATURES
• 5V±[128Kx8/64Kx16]0% for read, erase and write operation
[128Kx8/64Kx16]3[128Kx8/64Kx16]07[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16] [128Kx8/64Kx16]553[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16] switchable
• Fast access time:55[128Kx8/64Kx16]70[128Kx8/64Kx16]90[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]0ns
• Low power consumption
    - [128Kx8/64Kx16]0mA ma[128Kx8/64Kx16]imum active current(5MHz)
    - [128Kx8/64Kx16]uA typical standby current
• Command register architecture
    - Byte[128Kx8/64Kx16] Word Programming (7us[128Kx8/64Kx16] [128Kx8/64Kx16][128Kx8/64Kx16]us typical)
    - Erase ([128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-Byte[128Kx8/64Kx16][128Kx8/64Kx16], [128Kx8/64Kx16][128Kx8/64Kx16]-Byte[128Kx8/64Kx16][128Kx8/64Kx16], 3[128Kx8/64Kx16][128Kx8/64Kx16]-Byte[128Kx8/64Kx16][128Kx8/64Kx16], and [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-Byte [128Kx8/64Kx16][128Kx8/64Kx16])
• Auto Erase (chip) and Auto Program
    - Automatically erase any combination of sectors or with Erase Suspend capability.
    - Automatically program and verify data at specified address
• Status Reply
    - Data polling & Toggle bit for detection of program and erase cycle completion.
• Compatibility with JEDEC standard
    - Pinout and software compatible with single-power supply FLASH
    - Superior inadvertent write protection
• Sector protection
    - Hardware method to disable any combination of sectors from program or erase operations
    - Sector protect[128Kx8/64Kx16]unprotect for 5V only system or 5V[128Kx8/64Kx16] [128Kx8/64Kx16][128Kx8/64Kx16]V system
[128Kx8/64Kx16]00,000 minimum erase[128Kx8/64Kx16]program cycles
• Latch-up protected to [128Kx8/64Kx16]00mA from -[128Kx8/64Kx16] to VCC+[128Kx8/64Kx16]V
• Boot Code Sector Architecture
    - T = Top Boot Sector
    - B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.[128Kx8/64Kx16]V
• Pac[128Kx8/64Kx16]age type:
    - [128Kx8/64Kx16][128Kx8/64Kx16]-pin SOP
    - [128Kx8/64Kx16][128Kx8/64Kx16]-pin TSOP
• Ready[128Kx8/64Kx16]Busy pin(RY[128Kx8/64Kx16]BY)
    - Provides a hardware method or detecting program or erase cycle completion
• Erase suspend[128Kx8/64Kx16] Erase Resume
    - Suspend an erase operation to read data from, or program data to a sector that is not being erased, then resume the erase operation.
• Hardware RESET pin
    - Hardware method of resetting the device to reading the device to reading array data.
[128Kx8/64Kx16]0 years data retention<[128Kx8/64Kx16]p>

Part Name(s) : M[128KX8/64KX16]MGB[128KX8/64KX16][128KX8/64KX16][128KX8/64KX16]S[128KX8/64KX16]BVP M[128KX8/64KX16]MGB_T[128KX8/64KX16][128KX8/64KX16][128KX8/64KX16]S[128KX8/64KX16]BVP M[128KX8/64KX16]MGT[128KX8/64KX16][128KX8/64KX16][128KX8/64KX16]S[128KX8/64KX16]BVP M[128KX8/64KX16]MGB[128KX8/64KX16]T[128KX8/64KX16][128KX8/64KX16][128KX8/64KX16]S[128KX8/64KX16]BVP Mitsubishi
MITSUBISHI ELECTRIC
Description : [128Kx8/64Kx16][128Kx8/64Kx16],777,[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-BIT ([128Kx8/64Kx16],0[128Kx8/64Kx16][128Kx8/64Kx16],57[128Kx8/64Kx16] -WORD BY [128Kx8/64Kx16][128Kx8/64Kx16]-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & [128Kx8/64Kx16],[128Kx8/64Kx16]9[128Kx8/64Kx16],30[128Kx8/64Kx16]-BIT (5[128Kx8/64Kx16][128Kx8/64Kx16],[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-WORD BY [128Kx8/64Kx16]-BIT) CMOS SRAM Stac[128Kx8/64Kx16]ed-MCP (Multi Chip Pac[128Kx8/64Kx16]age) View

DESCRIPTION
The MITSUBISHI M[128Kx8/64Kx16]MGB[128Kx8/64Kx16]T[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]S[128Kx8/64Kx16]BVP is a Stac[128Kx8/64Kx16]ed Multi Chip Pac[128Kx8/64Kx16]age (S-MCP) that contents [128Kx8/64Kx16][128Kx8/64Kx16]M-bits FLASH MEMORY and [128Kx8/64Kx16]M-bits Static RAM in a [128Kx8/64Kx16][128Kx8/64Kx16]-pin TSOP (TYPE-I).
[128Kx8/64Kx16][128Kx8/64Kx16]M-bits FLASH MEMORY is a [128Kx8/64Kx16]0[128Kx8/64Kx16][128Kx8/64Kx16]57[128Kx8/64Kx16] words, 3.3V-only, and high performance non-volatile MEMORY fabricated by CMOS technology for the peripheral circuit and DINOR(DIvided bit-line NOR) architecture for the MEMORY cell.
[128Kx8/64Kx16]M-bits SRAM is a [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]words unsynchronous SRAM fabricated by silicon-gate CMOS technology.
M[128Kx8/64Kx16]MGB[128Kx8/64Kx16]T[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]S[128Kx8/64Kx16]BVP is suitable for the application of the mobile-communication-system to reduce both the mount space and weight.<[128Kx8/64Kx16]p>

FEATURES
• Access time                                        
                         FLASH MEMORY           90ns (Ma[128Kx8/64Kx16].)
                         SRAM                       [128Kx8/64Kx16]5ns (Ma[128Kx8/64Kx16].)
• Supply voltage                                 Vcc=[128Kx8/64Kx16].7 ~ 3.[128Kx8/64Kx16]V
• Ambient temperature                     
                         W version                  Ta=-[128Kx8/64Kx16]0 ~ [128Kx8/64Kx16]5°C
• Pac[128Kx8/64Kx16]age : [128Kx8/64Kx16][128Kx8/64Kx16]-pin TSOP (Type-I) , 0.[128Kx8/64Kx16]mm lead pitch<[128Kx8/64Kx16]p>

APPLICATION
   Mobile communication  products<[128Kx8/64Kx16]p>


Part Name(s) : M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16][128KX8/64KX16][128KX8/64KX16]5 MCNIX
Macronix International
Description : [128Kx8/64Kx16][128Kx8/64Kx16]M-BIT [[128Kx8/64Kx16]M [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]M [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]] CMOS SINGLE VOLTAGE FLASH EEPROM View

GENERAL DESCRIPTION
The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]5 is a [128Kx8/64Kx16][128Kx8/64Kx16]-mega bit FLASH MEMORY organized as either [128Kx8/64Kx16]M word[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16] or [128Kx8/64Kx16]M byte[128Kx8/64Kx16][128Kx8/64Kx16]. M[128Kx8/64Kx16]ICs FLASH memories offer the most cost-effective and reliable read[128Kx8/64Kx16] write non-volatile random access MEMORY. The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]5 is pac[128Kx8/64Kx16]aged in [128Kx8/64Kx16][128Kx8/64Kx16]-pin PDIP. It is designed to be reprogrammed and in standard EPROM programmers.<[128Kx8/64Kx16]p>

FEATURES
• 5V ± [128Kx8/64Kx16]0% write and erase
• JEDEC-standard EEPROM commands
• Endurance:[128Kx8/64Kx16]00 cycles
• Fast access time: 90[128Kx8/64Kx16][128Kx8/64Kx16]00[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]0ns
• Auto Erase and Auto Program Algorithms
    - Automatically erases the whole chip
    - Automatically programs and verifies data at specified addresses
• Status Register feature for detection of program or erase cycle completion
• Low VCC write inhibit is equal to or less than 3.[128Kx8/64Kx16]V
• Software and hardware data protection
• Page program operation
    - Internal address and data latches for [128Kx8/64Kx16][128Kx8/64Kx16] words per page
    - Page programming time: 0.9ms typical
• Low power dissipation
    - 30mA typical active current
    - [128Kx8/64Kx16]uA typical standby current
CMOS and TTL compatible inputs and outputs
• Pac[128Kx8/64Kx16]age Type:
    - [128Kx8/64Kx16][128Kx8/64Kx16] lead PDIP<[128Kx8/64Kx16]p>

Part Name(s) : M[128KX8/64KX16][128KX8/64KX16]9F[128KX8/64KX16][128KX8/64KX16][128KX8/64KX16]5 Macronix
Macronix International
Description : [128Kx8/64Kx16][128Kx8/64Kx16]M-BIT [[128Kx8/64Kx16]M [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]M [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]] CMOS SINGLE VOLTAGE FLASH EEPROM View

GENERAL DESCRIPTION
The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]5 is a [128Kx8/64Kx16][128Kx8/64Kx16]-mega bit FLASH MEMORY organized as either [128Kx8/64Kx16]M word[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16] or [128Kx8/64Kx16]M byte[128Kx8/64Kx16][128Kx8/64Kx16]. M[128Kx8/64Kx16]ICs FLASH memories offer the most cost-effective and reliable read[128Kx8/64Kx16] write non-volatile random access MEMORY. The M[128Kx8/64Kx16][128Kx8/64Kx16]9F[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]5 is pac[128Kx8/64Kx16]aged in [128Kx8/64Kx16][128Kx8/64Kx16]-pin PDIP. It is designed to be reprogrammed and in standard EPROM programmers.<[128Kx8/64Kx16]p>

FEATURES
• 5V ± [128Kx8/64Kx16]0% write and erase
• JEDEC-standard EEPROM commands
• Endurance:[128Kx8/64Kx16]00 cycles
• Fast access time: 90[128Kx8/64Kx16][128Kx8/64Kx16]00[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]0ns
• Auto Erase and Auto Program Algorithms
    - Automatically erases the whole chip
    - Automatically programs and verifies data at specified addresses
• Status Register feature for detection of program or erase cycle completion
• Low VCC write inhibit is equal to or less than 3.[128Kx8/64Kx16]V
• Software and hardware data protection
• Page program operation
    - Internal address and data latches for [128Kx8/64Kx16][128Kx8/64Kx16] words per page
    - Page programming time: 0.9ms typical
• Low power dissipation
    - 30mA typical active current
    - [128Kx8/64Kx16]uA typical standby current
CMOS and TTL compatible inputs and outputs
• Pac[128Kx8/64Kx16]age Type:
    - [128Kx8/64Kx16][128Kx8/64Kx16] lead PDIP<[128Kx8/64Kx16]p>

Part Name(s) : [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLNIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLNIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLAIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLNIG [128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLSIG W[128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BL W[128KX8/64KX16]5[128KX8/64KX16][128KX8/64KX16]0BLSNIG Winbond
Winbond
Description : [128Kx8/64Kx16]M-BIT<[128Kx8/64Kx16]font>, [128Kx8/64Kx16]M-BIT AND [128Kx8/64Kx16]M-BIT [128Kx8/64Kx16].5V SERIAL FLASH MEMORY WITH [128Kx8/64Kx16][128Kx8/64Kx16]B SECTORS AND DUAL I[128Kx8/64Kx16]O SPI View

GENERAL DESCRIPTION
[128Kx8/64Kx16]>
The W[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]0BL ([128Kx8/64Kx16]M-BIT<[128Kx8/64Kx16]font>), W[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]0BL ([128Kx8/64Kx16]M-bit) and the W[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]0BL ([128Kx8/64Kx16]M-bit) Serial FLASH memories provides a storage solution for systems with limited space, pins and power. The [128Kx8/64Kx16]5[128Kx8/64Kx16] series offers fle[128Kx8/64Kx16]ibility and performance well beyond ordinary Serial FLASH devices. They are ideal for code download applications as well as storing voice, te[128Kx8/64Kx16]t and data. The devices operate on a single [128Kx8/64Kx16].3V to 3.[128Kx8/64Kx16]V power supply with current consumption as low as [128Kx8/64Kx16]mA active and [128Kx8/64Kx16]µA for power-down. All devices are offered in space-saving pac[128Kx8/64Kx16]ages.<[128Kx8/64Kx16]p>


[128Kx8/64Kx16]
>
FEATURES
[128Kx8/64Kx16]>
• Family of Serial FLASH Memories
[128Kx8/64Kx16]>
– W[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]0BL: [128Kx8/64Kx16]M-BIT<[128Kx8/64Kx16]font>[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-byte ([128Kx8/64Kx16]3[128Kx8/64Kx16],07[128Kx8/64Kx16])
[128Kx8/64Kx16]
>
– W[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]0BL: [128Kx8/64Kx16]M-bit[128Kx8/64Kx16][128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]-byte ([128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16],[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16])
[128Kx8/64Kx16]>
– W[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16]0BL: [128Kx8/64Kx16]M-bit[128Kx8/64Kx16]5[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-byte (5[128Kx8/64Kx16][128Kx8/64Kx16],[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16])
[128Kx8/64Kx16]>
[128Kx8/64Kx16]5[128Kx8/64Kx16]-bytes per programmable page
[128Kx8/64Kx16]>
– Uniform [128Kx8/64Kx16][128Kx8/64Kx16]B Sectors, 3[128Kx8/64Kx16][128Kx8/64Kx16]B & [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]B Bloc[128Kx8/64Kx16]s
[128Kx8/64Kx16]>
• SPI with Single [128Kx8/64Kx16] Dual Outputs [128Kx8/64Kx16] Dual I[128Kx8/64Kx16]O
[128Kx8/64Kx16]>
– Cloc[128Kx8/64Kx16], Chip Select, Data I[128Kx8/64Kx16]O, Data Out
[128Kx8/64Kx16]>
– Optional Hold function for SPI fle[128Kx8/64Kx16]ibility
[128Kx8/64Kx16]>
• Data Transfer up to [128Kx8/64Kx16]00M-bits [128Kx8/64Kx16] second
[128Kx8/64Kx16]>
– Cloc[128Kx8/64Kx16] operation to 50MHz
[128Kx8/64Kx16]>
– Fast Read Dual Output instruction
[128Kx8/64Kx16]>
– Auto-increment Read capability
[128Kx8/64Kx16]>
• Efficient “Continuous Read Mode”
[128Kx8/64Kx16]>
– Low Instruction overhead
[128Kx8/64Kx16]>
– Continuous Read
[128Kx8/64Kx16]>
– As few as [128Kx8/64Kx16] cloc[128Kx8/64Kx16]s to address MEMORY
[128Kx8/64Kx16]>
– Allows true [128Kx8/64Kx16]IP (e[128Kx8/64Kx16]ecute in place) operation
[128Kx8/64Kx16]>
• Software and Hardware Write Protection
[128Kx8/64Kx16]>
– Write-Protect all or portion of MEMORY
[128Kx8/64Kx16]>
– Enable[128Kx8/64Kx16]Disable protection with [128Kx8/64Kx16]WP pin
[128Kx8/64Kx16]>
– Top or bottom array protection
[128Kx8/64Kx16]>
– Volatile & Non-volatile Status Register Bits
[128Kx8/64Kx16]>
• Fle[128Kx8/64Kx16]ible Architecture with [128Kx8/64Kx16][128Kx8/64Kx16]B sectors
[128Kx8/64Kx16]>
– Sector Erase ([128Kx8/64Kx16][128Kx8/64Kx16]-bytes)
[128Kx8/64Kx16]>
– Bloc[128Kx8/64Kx16] Erase (3[128Kx8/64Kx16][128Kx8/64Kx16] and [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-byte)
[128Kx8/64Kx16]>
– Page program up to [128Kx8/64Kx16]5[128Kx8/64Kx16] bytes <[128Kx8/64Kx16]ms
[128Kx8/64Kx16]>
– More than [128Kx8/64Kx16]00,000 erase[128Kx8/64Kx16]write cycles
[128Kx8/64Kx16]>
– More than [128Kx8/64Kx16]0-year retention
[128Kx8/64Kx16]>
• Low Power Consumption, Wide
[128Kx8/64Kx16]>
Temperature Range
[128Kx8/64Kx16]>
– Single [128Kx8/64Kx16].3 to 3.[128Kx8/64Kx16]V supply
[128Kx8/64Kx16]>
[128Kx8/64Kx16]mA active current, [128Kx8/64Kx16]µA Power-down (typ)
[128Kx8/64Kx16]>
– -[128Kx8/64Kx16]0° to +[128Kx8/64Kx16]5°C operating range
[128Kx8/64Kx16]>
• Space Efficient Pac[128Kx8/64Kx16]aging
[128Kx8/64Kx16]>
[128Kx8/64Kx16]-pin SOIC [128Kx8/64Kx16]50-mil
[128Kx8/64Kx16]>
[128Kx8/64Kx16]-pin SOIC [128Kx8/64Kx16]0[128Kx8/64Kx16]-mil
[128Kx8/64Kx16]>
[128Kx8/64Kx16]-pad WSON [128Kx8/64Kx16][128Kx8/64Kx16]5-mm
[128Kx8/64Kx16]>
[128Kx8/64Kx16]-pin PDIP 300-mil<[128Kx8/64Kx16]p>

Part Name(s) : M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16] M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]TC-70 M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]TC-90 M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]TI-70 M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]TI-90 Macronix
Macronix International
Description : [128Kx8/64Kx16]M-BIT [[128Kx8/64Kx16]M [128Kx8/64Kx16] [128Kx8/64Kx16]] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY View

GENERAL DESCRIPTION
The M[128Kx8/64Kx16][128Kx8/64Kx16]9LV0[128Kx8/64Kx16][128Kx8/64Kx16] is a [128Kx8/64Kx16]-mega bit FLASH MEMORY organized as [128Kx8/64Kx16]M bytes of [128Kx8/64Kx16] bits. M[128Kx8/64Kx16]ICs FLASH memories offer the most cost-effective and reliable read[128Kx8/64Kx16]write nonvolatile random access MEMORY. The M[128Kx8/64Kx16][128Kx8/64Kx16]9LV0[128Kx8/64Kx16][128Kx8/64Kx16] is pac[128Kx8/64Kx16]aged in [128Kx8/64Kx16]0-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
<[128Kx8/64Kx16]p>

FEATURES
• Status Reply
    - Data polling & Toggle bit for detection of program and erase operation completion.
• Ready[128Kx8/64Kx16]Busy pin (RY[128Kx8/64Kx16]BY)
    - Provides a hardware method of detecting program or erase operation completion.
• Sector protection
    - Hardware method to disable any combination of sectors from program or erase operations
    - Any combination of sectors can be erased with erase suspend[128Kx8/64Kx16]resume function.
    - Tempoary sector unprotect allows code changes in previously loc[128Kx8/64Kx16]ed sectors.
[128Kx8/64Kx16]00,000 minimum erase[128Kx8/64Kx16]program cycles
• Latch-up protected to [128Kx8/64Kx16]00mA from -[128Kx8/64Kx16]V to VCC+[128Kx8/64Kx16]
• Low VCC write inhibit is equal to or less than [128Kx8/64Kx16].3V
• Pac[128Kx8/64Kx16]age type:
    - [128Kx8/64Kx16]0-pin TSOP
• Compatibility with JEDEC standard
    - Pinout and software compatible with single-power supply FLASH
• E[128Kx8/64Kx16]tended single - supply voltage range [128Kx8/64Kx16].7V to 3.[128Kx8/64Kx16]V
[128Kx8/64Kx16],0[128Kx8/64Kx16][128Kx8/64Kx16],57[128Kx8/64Kx16] [128Kx8/64Kx16] [128Kx8/64Kx16]
• Single power supply operation
    - 3.0V only operation for read, erase and program operation
• Fast access time: 70[128Kx8/64Kx16]90ns
• Low power consumption
    - [128Kx8/64Kx16]0mA ma[128Kx8/64Kx16]imum active current
    - 0.[128Kx8/64Kx16]uA typical standby current
• Command register architecture
    - Byte[128Kx8/64Kx16]word Programming (7us[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]us typical)
    - Sector Erase (Sector structure [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-Byte [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16])
• Auto Erase (chip & sector) and Auto Program
    - Automatically erase any combination of sectors with Erase Suspend capability.
    - Automatically program and verify data at specified address
• Erase suspend[128Kx8/64Kx16]Erase Resume
    - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase.<[128Kx8/64Kx16]p>

Part Name(s) : M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]B M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]BTC-70 M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]BTC-90 M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]BTI-70 M[128KX8/64KX16][128KX8/64KX16]9LV0[128KX8/64KX16][128KX8/64KX16]BTI-90 Macronix
Macronix International
Description : [128Kx8/64Kx16]M-BIT [[128Kx8/64Kx16]M [128Kx8/64Kx16] [128Kx8/64Kx16]] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY View

GENERAL DESCRIPTION
The M[128Kx8/64Kx16][128Kx8/64Kx16]9LV0[128Kx8/64Kx16][128Kx8/64Kx16]B is a [128Kx8/64Kx16]-mega bit FLASH MEMORY organized as [128Kx8/64Kx16]M bytes of [128Kx8/64Kx16] bits. M[128Kx8/64Kx16]ICs FLASH memories offer the most cost-effective and reliable read[128Kx8/64Kx16]write nonvolatile random access MEMORY. The M[128Kx8/64Kx16][128Kx8/64Kx16]9LV0[128Kx8/64Kx16][128Kx8/64Kx16]B is pac[128Kx8/64Kx16]aged in [128Kx8/64Kx16]0-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.<[128Kx8/64Kx16]p>

FEATURES
• Status Reply
    - Data polling & Toggle bit for detection of program and erase operation completion.
• Ready[128Kx8/64Kx16]Busy pin (RY[128Kx8/64Kx16]BY)
    - Provides a hardware method of detecting program or erase operation completion.
• Sector protection
    - Hardware method to disable any combination of sectors from program or erase operations
    - Any combination of sectors can be erased with erase suspend[128Kx8/64Kx16]resume function.
    - Temporary sector unprotect allows code changes in previously loc[128Kx8/64Kx16]ed sectors.
[128Kx8/64Kx16]00,000 minimum erase[128Kx8/64Kx16]program cycles
• Latch-up protected to [128Kx8/64Kx16]00mA from -[128Kx8/64Kx16]V to VCC+[128Kx8/64Kx16]
• Pac[128Kx8/64Kx16]age type:
    - [128Kx8/64Kx16]0-pin TSOP
• Compatibility with JEDEC standard
    - Pinout and software compatible with single-power supply FLASH
[128Kx8/64Kx16]0 years data retention
• E[128Kx8/64Kx16]tended single - supply voltage range [128Kx8/64Kx16].7V to 3.[128Kx8/64Kx16]V
[128Kx8/64Kx16],0[128Kx8/64Kx16][128Kx8/64Kx16],57[128Kx8/64Kx16] [128Kx8/64Kx16] [128Kx8/64Kx16]
• Single power supply operation
    - 3.0V only operation for read, erase and program operation
• Fast access time: 70[128Kx8/64Kx16]90ns
• Low power consumption
    - [128Kx8/64Kx16]0mA ma[128Kx8/64Kx16]imum active current
    - 0.[128Kx8/64Kx16]uA typical standby current
• Fully compatible with M[128Kx8/64Kx16][128Kx8/64Kx16]9LV0[128Kx8/64Kx16][128Kx8/64Kx16] device
• Command register architecture
    - Byte[128Kx8/64Kx16]word Programming (7us[128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]us typical)
    - Sector Erase (Sector structure [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16]-Byte [128Kx8/64Kx16][128Kx8/64Kx16][128Kx8/64Kx16])
• Auto Erase (chip & sector) and Auto Program
    - Automatically erase any combination of sectors with Erase Suspend capability.
    - Automatically program and verify data at specified address
• Erase suspend[128Kx8/64Kx16]Erase Resume
    - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase.<[128Kx8/64Kx16]p>

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