Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

P/N + Description + Content Search

Search Word's :
Description : In-System Programmable SuperFASTHigh Density PLD

Description

The ispLSI 2064E is a High Density Programmable Logic Device. The device contains 64 Registers, 64 Universal I/O pins, four Dedicated Input Pins, three Dedicated Clock Input Pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064E features 5V In-System programmability and In-System diagnostic capabilities. The ispLSI 2064E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.



Features

SuperFAST High Density In-System Programmable LOGIC

   — 2000 PLD Gates

   — 64 I/O Pins, Four Dedicated Inputs

   — 64 Registers

   — High Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

   — 100% Functionally and JEDEC Upward Compatible with ispLSI 2064 Devices

High PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 200 MHz Maximum Operating Frequency

   — tpd = 4.5 ns Propagation Delay

   — TTL Compatible Inputs and Outputs

   — 5V Programmable Logic Core

   — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port

   — User-Selectable 3.3V or 5V I/O Supports Mixed Voltage Systems

   — PCI Compatible Outputs

   — Open-Drain Output Option

   — Electrically Erasable and ReProgrammable

   — Non-Volatile

   — Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

   — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

   — Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS

   — Complete Programmable Device Can Combine Glue Logic and Structured Designs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control to Minimize Switching Noise

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH In-System PROGRAMMING

   — Superior Quality of Results

   — Tightly Integrated with Leading CAE Vendor Tools

   — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™

   — PC and UNIX Platforms



 


Description : In-System Programmable SuperFASTHigh Density PLD

Description

The ispLSI 2128E is a High Density Programmable Logic Device. The device contains 128 Registers, 128 Univer sal I/O pins, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128E features 5V In-System programmability and In-System diagnostic capabilities. The ispLSI 2128E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable systems.



Features

SuperFAST High Density In-System Programmable LOGIC

   — 6000 PLD Gates

   — 128 I/O Pins, Eight Dedicated Inputs

   — 128 Registers

   — High Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

   — 100% Functional/JEDEC Upward Compatible with ispLSI 2128 Devices

High PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 180 MHz Maximum Operating Frequency

   — tpd = 5.0 ns Propagation Delay

   — TTL Compatible Inputs and Outputs

   — 5V Programmable Logic Core

   — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port

   — User-Selectable 3.3V or 5V I/O Supports Mixed Voltage Systems

   — PCI Compatible Outputs

   — Open-Drain Output Option

   — Electrically Erasable and ReProgrammable

   — Non-Volatile

   — Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

   — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

   — Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS

   — Complete Programmable Device Can Combine Glue Logic and Structured Designs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control to Minimize Switching Noise

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH In-System PROGRAMMING

   — Superior Quality of Results

   — Tightly Integrated with Leading CAE Vendor Tools

   — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™

   — PC and UNIX Platforms



 


Description : In-System Programmable SuperFAST High Density PLD

Description

The ispLSI 2096E is a High Density Programmable Logic Device. The device contains 96 Registers, 96 Universal I/O pins, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096E features 5V In-System programmability and In-System diagnostic capabilities. The ispLSI 2096E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable systems.



Features

SuperFAST High Density In-System Programmable LOGIC

   — 4000 PLD Gates

   — 96 I/O Pins, Six Dedicated Inputs

   — 96 Registers

   — High Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

   — 100% Functional/JEDEC Upward Compatible with ispLSI 2096 Devices

High PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 180 MHz Maximum Operating Frequency

   — tpd = 5.0 ns Propagation Delay

   — TTL Compatible Inputs and Outputs

   — 5V Programmable Logic Core

   — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port

   — User-Selectable 3.3V or 5V I/O Supports MixedVoltage Systems

   — PCI Compatible Outputs

   — Open-Drain Output Option

   — Electrically Erasable and ReProgrammable

   — Non-Volatile

   — Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

   — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

   — Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS

   — Complete Programmable Device Can Combine Glue Logic and Structured Designs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control to Minimize Switching Noise

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity



 


Description : 2.5V In-System Programmable SuperFASTHigh Density PLD

Description
The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).
   
Features
SuperFAST High Density Programmable LOGIC
    — 2000 PLD Gates
    — 64 and 32 I/O Pin Versions, Four Dedicated Inputs
    — 64 Registers
    — High Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State
        Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
    — 100% Functional, JEDEC and Pinout Compatible with
        ispLSI 2064V and 2064VE Devices
2.5V LOW VOLTAGE 2064 ARCHITECTURE
    — Interfaces with Standard 3.3V TTL Devices (Inputs
        and I/Os are 3.3V Tolerant)
    — 60 mA Typical Active Current
High-PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 165MHz Maximum Operating Frequency
    — tpd = 5.5ns Propagation Delay
    — Electrically Erasable and ReProgrammable
    — Non-Volatile
    — 100% Tested at Time of Manufacture
    — Unused Product Term Shutdown Saves Power
In-System Programmable
    — 2.5V In-System Programmability (ISP™) Using
        Boundary Scan Test Access Port (TAP)
    — Open-Drain Output Option for Flexible Bus Interface
        Capability, Allowing Easy Implementation of Wired-OR
        or Bus Arbitration Logic
    — Increased Manufacturing Yields, Reduced Time-toMarket
        and Improved Product Quality
    — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
    PLDs WITH THE Density AND FLEXIBILITY OF FPGAs
    — Enhanced Pin Locking Capability
    — Three Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Programmable Output Slew Rate Control
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global
        Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE
    ISP DEVICE DESIGN SYSTEMS FROM HDL
    SYNTHESIS THROUGH In-System PROGRAMMING
    — Superior Quality of Results
    — Tightly Integrated with Leading CAE Vendor Tools
    — Productivity Enhancing Timing Analyzer, Explore
        Tools, Timing Simulator and ispANALYZER™
    — PC and UNIX Platforms
   

Description : In-System Programmable SuperFASTHigh Density PLD

Description

The ispLSI 2032E is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V In-System programmability and In-System diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.



Features

SuperFAST High Density In-System Programmable LOGIC

   — 1000 PLD Gates

   — 32 I/O Pins, Two Dedicated Inputs

   — 32 Registers

   — High Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

   — 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices

High PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 225 MHz Maximum Operating Frequency

   — tpd = 3.5 ns Propagation Delay

   — TTL Compatible Inputs and Outputs

   — 5V Programmable Logic Core

   — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port

   — User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems

   — PCI Compatible Outputs (48-Pin Package Only)

   — Open-Drain Output Option

   — Electrically Erasable and ReProgrammable

   — Non-Volatile

   — Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

   — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

   — Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS

   — Complete Programmable Device Can Combine Glue Logic and Structured Designs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control to Minimize Switching Noise

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity



 


Description : 2.5V In-System Programmable SuperFASTHigh Density PLD

Description

The ispLSI 2032VL is a High Density Programmable Logic Device containing 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VL features In-System programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VL offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.



Features

SuperFAST High Density In-System Programmable LOGIC

   — 1000 PLD Gates

   — 32 I/O Pins, Two Dedicated Inputs

   — 32 Registers

   — High Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

   — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V and 2032VE Devices

2.5V LOW VOLTAGE 2032 ARCHITECTURE

   — Interfaces With Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant)

   — 45 mA Typical Active Current

High PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 180 MHz Maximum Operating Frequency

   — tpd = 5.0 ns Propagation Delay

   — Electrically Erasable and ReProgrammable

   — Non-Volatile

   — 100% Tested at Time of Manufacture

   — Unused Product Term Shutdown Saves Power

In-System Programmable

   — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)

   — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic

   — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

   — Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FPGAs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH In-System PROGRAMMING

   — Superior Quality of Results

   — Tightly Integrated with Leading CAE Vendor Tools

   — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™

   — PC and UNIX Platforms



 


Description : 2.5V In-System Programmable SuperFASTHigh Density PLD

Description
The ispLSI 2128VL is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions.

Features
SuperFAST High Density In-System
   Programmable LOGIC
   — 6000 PLD Gates
   — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
   — 128 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State
      Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
   — 100% Functional, JEDEC and Pinout Compatible
      with ispLSI 2128V and 2128VE Devices
2.5V LOW VOLTAGE 2128 ARCHITECTURE
   — Interfaces with Standard 3.3V Devices (Inputs and
      I/Os are 3.3V Tolerant)
   — 125 mA Typical Active Current
High PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 150 MHz Maximum Operating Frequency
   — tpd = 6.0 ns Propagation Delay
   — Electrically Erasable and ReProgrammable
   — Non-Volatile
   — 100% Tested at Time of Manufacture
   — Unused Product Term Shutdown Saves Power
In-System Programmable
   — 2.5V In-System Programmability (ISP™) Using
      Boundary Scan Test Access Port (TAP)
   — Open-Drain Output Option for Flexible Bus Interface
      Capability, Allowing Easy Implementation of Wired
      OR Bus Arbitration Logic
   — Increased Manufacturing Yields, Reduced Time-to
      Market and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
   PLDs WITH THE Density AND FLEXIBILITY OF FPGAS
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global
      Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
   PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
   SYNTHESIS THROUGH In-System PROGRAMMING
   — Superior Quality of Results
   — Tightly Integrated with Leading CAE Vendor Tools
   — Productivity Enhancing Timing Analyzer, Explore
      Tools, Timing Simulator and ispANALYZER™
   — PC and UNIX Platforms

Part Name(s) : ISPLSI1016
Lattice
Lattice Semiconductor
Description : In-System Programmable High Density PLD

Description

The ispLSI 1016E is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E offers 5V non-volatile In-System programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin.

The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device. Each GLB has 18 inputs, a Programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.



Features

High-Density Programmable LOGIC

   — 2000 PLD Gates

   — 32 I/O Pins, Four Dedicated Inputs

   — 96 Registers

   — High-Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

High-PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 125 MHz Maximum Operating Frequency

   — tpd = 7.5 ns Propagation Delay

   — TTL Compatible Inputs and Outputs

   — Electrically Erasable and ReProgrammable

   — Non-Volatile

   — 100% Tested at Time of Manufacture

   — Unused Product Term Shutdown Saves Power

In-System Programmable

   — In-System Programmable (ISP™) 5V Only

   — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

   — Reprogram Soldered Device for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS

   — Complete Programmable Device Can Combine Glue Logic and Structured Designs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control to Minimize Switching Noise

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity

   — Lead-Free Package Options



 


Description : 3.3V In-System Programmable SuperFASTHigh Density PLD

Description
The ispLSI 2096VE is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VE features In-System programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

Features
SuperFAST High Density Programmable LOGIC
    — 4000 PLD Gates
    — 96 I/O Pins, Six Dedicated Inputs
    — 96 Registers
    — High Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
    — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V Devices
    — Pinout Compatible with ispLSI 2192VE
• 3.3V LOW VOLTAGE 2096 ARCHITECTURE
    — Interfaces with Standard 5V TTL Devices
High PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 250MHz Maximum Operating Frequency
    — tpd = 4.0ns Propagation Delay
    — Electrically Erasable and ReProgrammable
    — Non-Volatile
    — 100% Tested at Time of Manufacture
    — Unused Product Term Shutdown Saves Power
In-System Programmable
    — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
    — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
    — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
    — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FPGAS
    — Enhanced Pin Locking Capability
    — Three Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Programmable Output Slew Rate Control
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
• LEAD-FREE PACKAGE OPTIONS

Description : 3.3V In-System Programmable High Density SuperFASTPLD

Description
The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features In-System programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.

Features
SuperFAST High Density Programmable LOGIC
    — 2000 PLD Gates
    — 64 and 32 I/O Pin Versions, Four Dedicated Inputs
    — 64 Registers
    — High Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
    — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
    — Interfaces with Standard 5V TTL Devices
High-PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 280MHz Maximum Operating Frequency
    — tpd = 3.5ns Propagation Delay
    — Electrically Erasable and ReProgrammable
    — Non-Volatile
    — 100% Tested at Time of Manufacture
    — Unused Product Term Shutdown Saves Power
In-System Programmable
    — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
    — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
    — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
    — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE Density AND FLEXIBILITY OF FPGAs
    — Enhanced Pin Locking Capability
    — Three Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Programmable Output Slew Rate Control
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
• LEAD-FREE PACKAGE OPTIONS

12345678910 Next



All Rights Reserved© datasheetq.com  [Privacy Policy ] [ Request Datasheet] [Contact Us]