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Part Name(s) : IBM025160 IBM025161 IBM025170 IBM025171 ETC
Unspecified
Description : 256K X 16 MULTIPORT VIDEO RAM / SSOG-64 JEDEC Standard View

This 4Mb dual port Video RAM (VRAM) consists of a Dynamic Random Access Memory (DRAM) organized as 256K x 16 interfaced to a Serial Register / Serial Access Memory (SAM) organized as 256 x 16.



The VRAM supports three basic operations:

Bidirectional Random Access to the DRAM, Bidirectional Serial Access to the SAM, and Bidirectional Data Transfer between any DRAM row and the SAM.



Full compatibility is provided between Half Depth SAM (256 x 16) and Full Depth SAM (512 x 16) by setting the VRAM in Serial Register Stop (SRS) mode with a stop address of 128 bit (or less).


Part Name(s) : 5962-8949703MMA 5962-8949703MTA 5962-8949703MXA 5962-8949703MZA 5962-8949704MMA 5962-8949704MTA 5962-8949704MXA 5962-8949704MZA MT42C4256 MT42C4256C-10 AUSTIN
Austin Semiconductor
Description : 256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM View

DESCRIPTION
The SMJ44C251B/MT42C4256 multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic random-access memory (DRAM) organized as 262144 words of 4 bits each interfaced to a serial-data register or serialaccess memory (SAM) organized as 512 words of 4 bits each. The SMJ44C251B/MT42C4256 supports three types of operation: random access to and from the DRAM, serial access to and from the serial register, and bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer operations, the SMJ44C251B/MT42C4256 can be accessed simultaneously and asynchronously from the DRAM and SAM ports.

FEATURES
• Class B High-Reliability Processing
DRAM: 262144 Words × 4 Bits SAM: 512 Words × 4 Bits
• Single 5-V Power Supply (±10% Tolerance)
• Dual Port Accessibility–Simultaneous and Asynchronous Access From the DRAM and SAM Ports
• Bidirectional-Data-Transfer Function Between the DRAM and the Serial-Data Register
• 4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many as Four Memory Address Locations Written per Cycle From an On-Chip Color Register
• Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design
• Enhanced Page-Mode Operation for Faster Access
• CAS-Before-RAS (CBR) and Hidden Refresh Modes
• All Inputs/Outputs and Clocks Are TTL Compatible
• Long Refresh Period: Every 8 ms (Max)
• Up to 33-MHz Uninterrupted Serial-Data Streams
• 3-State Serial I/Os Allow Easy Multiplexing of Video-Data Streams
• 512 Selectable Serial-Register Starting
• Split Serial-Data Register for Simplified Real-Time Register Reload

Part Name(s) : HY534256A HY534256AJ HY534256ALJ HY534256AS HY534256ALS Hynix
Hynix Semiconductor
Description : 256K x 4-bit CMOS DRAM View

256K x 4-bit CMOS DRAM

Part Name(s) : HY534256AJ HY534256AJS HY534256AJS-60 HY534256AJS-70 HY534256AJS-80 HY534256AL HY534256AL-60 HY534256AL-70 HY534256AL-80 HY534256ALJ Hyundai
Hyundai Micro Electronics
Description : 256K x 4-bit CMOS DRAM View

256K x 4-bit CMOS DRAM


Part Name(s) : MSM54V16282 MSM54V16282-60 MSM54V16282-60GS-K MSM54V16282-60TS-K MSM54V16282-70 MSM54V16282-70GS-K MSM54V16282-70TS-K MSM54V16282-XXGS-K MSM54V16282-XXTS-K OKI
Oki Electric Industry
Description : 262,144-Word x 16-Bit Multiport DRAM View

DESCRIPTION
The MSM54V16282 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously.
It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM54V16282 features block write and flash write functions on the RAM port, and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-flops.

FEATURES
• Single power supply: 3.3 V ±0.3 V
• Full TTL compatibility
• Multiport organization
    RAM : 256K word x 16 bits
    SAM : 512 word x 16 bits
• Fast page mode
• Write per bit
• Byte write
• Masked flash write
• Masked block write (8 columns)
• RAS only refresh
• CAS before RAS refresh
• CAS before RAS self-refresh
• Hidden refresh
• Serial read/write
• 512 tap location
• Bidirectional data transfer
• Split transfer
• Masked write transfer
• Refresh: 512 cycles/8 ms
• Package options:
   64-pin 525 mil plastic SSOP (SSOP64-P-525-0.80-K) (Product : MSM54V16282-xxGS-K)
   70/64-pin 400 mil plastic TSOP (Type II)(TSOPII70/64-P-400-0.65-K)(Product : MSM54V16282-xxTS-K)
                                                                                                xx indicates speed rank.

Part Name(s) : MSM514252A MSM514252A-10 MSM514252A-70 MSM514252A-80 MSM514252A-70ZS MSM514252A-80ZS MSM514252A-10ZS MSM514252A-70JS MSM514252A-80JS MSM514252A-10JS OKI
Oki Electric Industry
Description : 262,144-Word x 4-Bit Multiport DRAM View

DESCRIPTION
The MSM514252A is an 1-Mbit CMOS multiport DRAM composed of a 262,144-word by 4-bit dynamic RAM, and a 512-word by 4-bit static serial access memory, SAM port. The RAM port and SAM port operate independently and asynchronously.
The MSM514252A supports three types of operations: random access to and from the RAM port, high speed serial access to and from the SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. The RAM port and the SAM port can be accessed independently except when data is being transferred between them internally.

FEATURES
• Single power supply of 5 V ±10% with a built-in VBB generator
• All inputs and outputs: TTL compatible
• Multiport organization
    RAM port: 256K word x 4 bits
    SAM port: 512 word x 4 bits
• RAM port
    Fast page mode, Read-modify-write
    CAS before RAS refresh, Hidden refresh
    RAS only refresh, Standard write-per-bit
SAM port
    High speed serial
    Read/Write capability
    Fully static register
    512 tap location
• RAM-SAM bidirectional, Read/Write/Pseudo write, Real time read transfer
• Package options:
    28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) (Product : MSM514252A-xxZS)
    28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM514252A-xxJS)
                                                                                           xx indicates speed rank.

Part Name(s) : MSM5416262 MSM5416262-50 MSM5416262-60 MSM5416262-70 MSM5416262-50GS-K MSM5416262-60GS-K MSM5416262-70GS-K OKI
Oki Electric Industry
Description : 262,144-Word x 16-Bit Multiport DRAM View

DESCRIPTION
The MSM5416262 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously.

FEATURES
• Single power supply: 5 V ±10%
• Full TTL compatibility
• Multiport organization
    RAM : 256K word x 16 bits
    SAM : 512 word x 16 bits
• Fast page mode
• Write per bit
• Byte write
• Masked flash write
• RAS only refresh
• CAS before RAS refresh
• Hidden refresh
• Serial read/write
• 512 tap location
• Bidirectional data transfer
• Split transfer
• Masked write transfer
• Refresh: 512 cycles/8 ms
• Masked block write (4 x 4 x 4)
• Package:
    64-pin 525 mil plastic SSOP (SSOP64-P-525-0.80-K) (Product : MSM5416262-xxGS-K) xx indicates speed rank.

Part Name(s) : MSM518122 MSM518122-70 MSM518122-70ZS MSM518122-70JS MSM518122-80 MSM518122-80ZS MSM518122-80JS MSM518122-10 MSM518122-10ZS MSM518122-10JS OKI
Oki Electric Industry
Description : 131,072-Word x 8-Bit Multiport DRAM View

DESCRIPTION
The MSM518122 is an 1-Mbit CMOS multiport DRAM composed of a 131,072-word by 8-bit dynamic RAM and a 256-word by 8-bit SAM. Its RAM and SAM operate independently and asynchronously.
The MSM518122 supports three types of operation : random access to RAM port, high speed serial access to SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM518122 features the block write and flash write functions on the RAM port and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-flops.

FEATURES
• Single power supply: 5 V ±10%
• Full TTL compatibility
• Multiport organization
    RAM: 128K word x 8 bits
    SAM: 256 word x 8 bits
• Fast page mode
• Write per bit
• Masked flash write
• Masked block write
• RAS only refresh
• CAS before RAS refresh
• Hidden refresh
• Serial read/write
• 256 tap location
• Bidirectional data transfer
• Split transfer
• Masked write transfer
• Refresh: 512 cycles/8 ms
• Package options:
    40-pin 475 mil plastic ZIP (ZIP40-P-475-1.27) (Product : MSM518122-xxZS)
    40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM518122-xxJS)
                                                                           xx indicates speed rank.

Part Name(s) : MSM548262 MSM548262-60 MSM548262-60JS MSM548262-60TS-K MSM548262-70 MSM548262-70JS MSM548262-70TS-K MSM548262-80 MSM548262-80JS MSM548262-80TS-K OKI
Oki Electric Industry
Description : 262,144-Word x 8-Bit Multiport DRAM View

DESCRIPTION
The MSM548262 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and asynchronously.

FEATURES
• Single power supply: 5 V ±10%
• Full TTL compatibility
• Multiport organization
    RAM : 256K word x 8 bits
    SAM : 512 word x 8 bits
• Fast page mode
• Write per bit
• Masked flash write
• Masked block write
• RAS only refresh
• CAS before RAS refresh
• Hidden refresh
• Serial read/write
• 512 tap location
• Bidirectional data transfer
• Split transfer
• Masked write transfer
• Refresh: 512 cycles/8 ms
• Package options:
    40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM548262-xxJS)
    44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548262-xxTS-K)
                                                                                                                xx indicates speed rank.

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