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Motorola
Motorola => Freescale
Description : 64K x 18 Bit Synchronous Pipelined Cache Tag RAM

The MCM69T618 is a 1M–bit Synchronous fast static RAM with integrated Tag compare function. It is designed to address Tag RAM for 512KB, 1MB, or 2MB secondary Cache as well as to be used as a data RAM for 512KB Caches. This device is organized as 64K words of 18 bits each. It integrates input registers, output registers, Tag comparators, and high speed SRAM onto a single monolithic circuit for reduced parts count in Cache Tag RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
   
• MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle
• Single 3.3 V + 10%, – 5% Power Supply
• Pipelined Data Comparator
• Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path
• 64K x 18 Organization Supports Up to 2MB Cache
Synchronous Data Input Register Load Enable (DE)
• Internally Self–Timed Write Cycle
• ASynchronous Data I/O Output Enable (G)
• ASynchronous Match Output Enable (MG)
• 100–Pin TQFP Package
   

Description : 256K x 18 Sync Cache Tag

Functional Description
The GS84118 is a 256K x 18 high performance Synchronous SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with PentiumTM and other high performance CPUs.

Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode
Synchronous address, data I/O, and control inputs
Synchronous Data Enable (DE)
• ASynchronous Output Enable (OE)
• ASynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTag Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA: T:TQFP or B: BGA

Motorola
Motorola => Freescale
Description : 256K ASynchronous Secondary Cache Module for Pentium™

The MCM64AF32 is designed to provide 256K of aSynchronous L2 Cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The module is configured as 32K x 64 bits in a 160 pin card edge connector. The module uses eight Motorola 3.3 V 32K x 8 FSRAMs for the Cache memory, one Motorola 5 V 32K x 8 FSRAM for the Tag RAM, and an upper order address latch.
Eight write enables are provided for byte write control.
PD0–PD4 identify density and functionality.
This Cache module is plug and pin compatible with the other members of Motorola’s Triton chip set module family, the MCM72JG32SG66 (a 256K byte pipelined BurstRAM module) and the MCM72JG64SG66 (a 512K byte pipelined BurstRAM module).

• Low–Cost ASynchronous Solution for Triton Chip Set
• All Cache Data Inputs and Outputs are LVTTL (3.3 V I/O) Compatible
• All Tag I/Os are TTL Compatible
• Byte Write Capability
• Fast SRAM Access Times:15 ns for Data RAMs and Tag RAM
• Decoupling Capacitors for each Fast Static RAM and Logic Device
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• 160 Pin Card Edge Module
• Burndy Connector, Part Number: CELP2X80SC3Z48

Motorola
Motorola => Freescale
Description : 256K and 512K Pipelined BurstRAM™ Sedcondary Cache Module for Pentium™

The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high performance, 256K/512K L2 Cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The modules are configured as 32K x 64 and 64K x 64 bits in a 160 pin card edge memory module. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the Tag RAM.

• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM 9 ns for Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes
• I/Os are 3.3 V Compatible on Data RAMs
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Series 20 Ω Resistors for Noise Immunity

Motorola
Motorola => Freescale
Description : 256KB Secondary Cache Module With Tag and Optional Dirty for 486 Processor Systems

These 256K Byte Cache modules offer dual aSynchronous 32K x 32 banks of memory. There is a 16K x 8 Tag memory for main memory Cacheability up to 64 Megabytes. The MCM32N865 and MCM32P865 include a 16K x 1 common I/O dirty bit for writeback Cache capability.
   
• 64MB of Cacheable Memory
• Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz
Cache Bank Write, Byte Chip Enable, Bank Output Enable
• Decoupling Capacitors are Used for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• 5 V and 3.3 V Power Supplies are Supported
   

Description : BiCMOS StaticRAM 240K (16K x 15-BIT) Cache-Tag RAM For the Pentium™ Processor

DESCRIPTION:
The IDT71215 is a 245,760-bit Cache Tag StaticRAM, organized 16K x 15 and designed to support the Pentium and other Intel processors at bus speeds up to 66MHz. There are twelve common I/O Tag bits, with the remaining three bits used as status bits. A 12-bit comparator is on-chip to allow fast comparison of the twelve stored Tag bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address.
This high-speed MATCH signal, with tADM as fast as 8ns, provides the fastest possible enabling of secondary Cache accesses.

FEATURES:
• 16K x 15 Configuration
   – 12 Tag Bits
   – 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
• Match output uses Valid bit to qualify MATCH output
• High-Speed Address-to-Match comparison times
   – 8/9/10/12ns over commercial temperature range
• BRDY circuitry included inside the Cache-Tag for highest
   speed operation
• ASynchronous Read/Match operation with Synchronous
   Write and Reset operation
• Separate WE for the Tag bits and the Status bits
• Separate OE for the Tag bits, the Status bits, and BRDY
Synchronous RESET pin for invalidation of all Tag entries
• Dual Chip selects for easy depth expansion with no
   performance degredation
• I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins
• PWRDN pin to place device in low-power mode
• Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP)

Description : BiCMOS StaticRAM 240K (16K x 15-BIT) Cache-Tag RAM For PowerPC and RISC Processors

DESCRIPTION:

The IDT71216 is a 245,760-bit Cache Tag StaticRAM, organized 16K x 15 and designed to support PowerPC and other RISC processors at bus speeds up to 66MHz. There are twelve common I/O Tag bits, with the remaining three bits used as status bits. A 12-bit comparator is on-chip to allow fast comparison of the twelve stored Tag bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address.



FEATURES:

• 16K x 15 Configuration

  – 12 Tag Bits

  – 3 Separate I/O Status Bits (Valid, Dirty, Write Through)

• Match output uses Valid bit to qualify MATCH output

• High-Speed Address-to-Match comparison times

  – 8/9/10/12ns over commercial temperature range

• TA circuitry included inside the Cache-Tag for highest speed operation

• ASynchronous Read/Match operation with Synchronous Write and Reset operation

• Separate WE for the Tag bits and the Status bits

• Separate OE for the Tag bits, the Status bits, and TA

Synchronous RESET pin for invalidation of all Tag entries

• Dual Chip selects for easy depth expansion with no performance degredation

• I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins

• PWRDN pin to place device in low-power mode

• Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP)


Description : 256K x 18 Sync Cache Tag

Functional Description
The GS84118A is a 256K x 18 high performance Synchronous SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with PentiumTM and other high performance CPUs.

Features
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode
Synchronous address, data I/O, and control inputs
Synchronous Data Enable (DE)
• ASynchronous Output Enable (OE)
• ASynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTag Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP and 119-BGA packages
• Pb-Free 100-lead TQFP package available

Description : 256K x 18 Synchronous-Pipelined Cache RAM

Functional Description
The CY7C1327B is a 3.3V, 256K by 18 Synchronous-pipelined Cache SRAM designed to support zero wait state secondary Cache with minimal glue logic.

Features
• Supports 100-MHz bus for Pentium® and PowerPC™ operations with zero wait states
• Fully registered inputs and outputs for pipelined operation
256K by 18 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
    — 3.5 ns (for 166-MHz device)
    — 4.0 ns (for 133-MHz device)
    — 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
Synchronous self-timed writes
• ASynchronous Output Enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option

Description : 256K x 18 Synchronous 3.3V Cache RAM

Functional Description
The CY7C1325B is a 3.3V, 256K by 18 Synchronous Cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• Supports 117-MHz microprocessor Cache systems with zero wait states
256K by 18 common I/O
• Fast clock-to-output times
    — 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either interleaved or linear burst sequence
• Separate processor and controller address strobes provide direct interface with the processor and external Cache controller
Synchronous self-timed write
• ASynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode

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