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PRODUCT OVERVIEW
The DD28F032SA is a high-performance 32-MBIT (33,554,432-bit) block erasable nonvolatile random access MEMORY organized as either 2 Mword x 16, or 4 Mbyte x 8. The DD28F032SA is built using two 28F016SA chips encapsulated in a single 56- lead TSOP Type I package. The DD28F032SA includes sixty-four 64-KB (65,536) blocks or sixtyfour 32-KW (32,768) blocks.

■ User-Selectable 3.3V or 5V VCC
■ User-Configurable x8 or x16 Operation
■ 70 ns Maximum Access Time
■ 28.6 MB/sec Burst Write Transfer Rate
■ 1 Million Typical Erase Cycles per Block
■ 56-Lead, 1.2 x 14 x 20 mm Advanced Dual Die TSOP Package Technology
■ 64 Independently Lockable Blocks
■ Revolutionary Architecture
    - 100% Backwards-Compatible with Intel 28F016SA
    - Pipelined Command Execution
    - Program during Erase
■ 2 mA Typical ICC in Static Mode
■ 2 µA Typical Deep Power-Down
■ State-of-the-Art 0.6 µm ETOX™ IV Flash Technology

Intel’s VS/MS28F016SV, 16-Mbit FlashFiIeTM MEMORY is the latest member of Intel’s high density, high performance MEMORY family for the Industrial, Special Environment, and Military markets. Its user selectable VCC and VPP (SmartVoltage Technology), innovative capabilities, 100% compatibility with the VE28F008 and M28F008, multiple power savings modes, selective block locking, and very fast read/write performance make it the ideal choice for any applications that need a high density and a wide temperature range MEMORY device. The VS/MS28F016SV is the ideal choice for designers who need to break free from the dependence on slow rotating media or battery backed up MEMORY arrays.
   
■ VS28F016SV
    — -40°C to +125°C
    — SE2 Grade
■ MS28F016SV
    — -55°C to +125°C
    — QML Certified
    — SE1 Grade
■ SmartVoltage Technology
    — User-Selectable 3.3V or 5V VCC
    — User-Selectable 5V or 12V VPP
■ Three Voltage/Speed Options
    — 80 ns Access Time, 5.0V ±5%
    — 85 ns Access Time, 5.0V ±10%
    — 120 ns Access Time, 3.3V ±10%
■ 1 Million Erase Cycles per Block
    Typical
■ 14.3 MB/sec Burst Write Transfer Rate
■ Configurable x8 or x16 Operation
■ 56-Lead SSOP Plastic Package
■ Backwards-Compatible with VE28F008,
    M28F008 and 28F016SA Command Set
■ Revolutionary Architecture
    — Multiple Command Execution
    — Write During Erase
    — Command Super-Set of the Intel
        VE28F008, M28F008
    — Page Buffer Write
■ Multiple Power Savings Modes
■ Two 256-Byte Page Buffers
■ State-of-the-Art 0.6 μm ETOX™ IV
    Flash Technology
   

16 Mbit(1 Mbit x 16, 2 Mbit x 8) Flash MEMORY

16 Mbit(1 Mbit x 16, 2 Mbit x 8) 5V Single Voltage Flash MEMORY

INTRODUCTION
The specifications intended to give an overview of the chip feature-set and of the operating AC/DC specifications. Please refer to Users Manual also, to leam detail usage.

Description
The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip Package:
● a 64-Mbit, Multiple Bank Flash MEMORY, the M58WR064HT/B, and
● a 32-MBIT Pseudo SRAM, the M69KB048BD.
The purpose of this document is to describe how the two MEMORY components operate with respect to each other. It must be read in conjunction with the M58WR064HT/B and M69KB048BD datasheets, where all specifications required to operate the Flash MEMORY and PSRAM components are fully detailed. These datasheets are available from the ST web site: www.st.com.

Features
■ Multi-Chip Package
    – 1 die of 64 Mbit (4 Mb × 16) Flash MEMORY
    – 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM
■ Supply voltage
    – VDDF = VDDP = VDDQF = 1.7 V to 1.95 V
■ Low power consumption
■ Electronic signature
    – Manufacturer Code: 20h
    – Device code (top flash configuration), M36W0R6050T1: 8810h
    – Device code (bottom flash configuration), M36W0R6050B1: 8811h
■ Package
    – ECOPACK®

Flash MEMORY
■ Programming time
    – 8 µs by Word typical for Fast Factory Program
    – Double/Quadruple Word Program option
    – Enhanced Factory Program options
■ MEMORY blocks
    – Multiple Bank MEMORY array: 4 Mbit Banks
    – Parameter Blocks (Top or Bottom location)
■ Synchronous / Asynchronous Read
    – Synchronous Burst Read mode: 66 MHz
    – Asynchronous/ Synchronous Page Read mode
    – Random Access: 70 ns
■ Dual operations
    – Program Erase in one Bank while Read in others
    – No delay between Read and Write operations
■ Block locking
    – All blocks locked at Power-up
    – Any combination of blocks can be locked
    – WPF for Block Lock-Down
■ Security
    – 128-bit user programmable OTP cells
    – 64-bit unique device number
■ Common Flash Interface (CFI)
■ 100 000 program/erase cycles per block

PSRAM
■ Access time: 70 ns
■ Asynchronous Page Read
    – Page size: 8 words
    – First access within page: 70 ns
    – Subsequent read within page: 20 ns
■ Three Power-down modes
    – Deep Power-Down
    – Partial Array Refresh of 4 Mbits
    – Partial Array Refresh of 8 Mbits

Description
The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip Package:
● a 64-Mbit, Multiple Bank Flash MEMORY, the M58WR064HT/B, and
● a 32-MBIT Pseudo SRAM, the M69KB048BD.
The purpose of this document is to describe how the two MEMORY components operate with respect to each other. It must be read in conjunction with the M58WR064HT/B and M69KB048BD datasheets, where all specifications required to operate the Flash MEMORY and PSRAM components are fully detailed. These datasheets are available from the Numonyx web site: www.numonyx.com.

Features
■ Multi-Chip Package
    – 1 die of 64 Mbit (4 Mb × 16) Flash MEMORY
    – 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM
■ Supply voltage
    – VDDF = VDDP = VDDQF = 1.7 V to 1.95 V
■ Low power consumption
■ Electronic signature
    – Manufacturer Code: 20h
    – Device code (top flash configuration), M36W0R6050T1: 8810h
    – Device code (bottom flash configuration), M36W0R6050B1: 8811h
■ Package
    – ECOPACK®

Flash MEMORY
■ Programming time
    – 8 µs by Word typical for Fast Factory Program
    – Double/Quadruple Word Program option
    – Enhanced Factory Program options
■ MEMORY blocks
    – Multiple Bank MEMORY array: 4 Mbit Banks
    – Parameter Blocks (Top or Bottom location)
■ Synchronous / Asynchronous Read
    – Synchronous Burst Read mode: 66 MHz
    – Asynchronous/ Synchronous Page Read mode
    – Random Access: 70 ns
■ Dual operations
    – Program Erase in one Bank while Read in others
    – No delay between Read and Write operations
■ Block locking
    – All blocks locked at Power-up
    – Any combination of blocks can be locked
    – WPF for Block Lock-Down
■ Security
    – 128-bit user programmable OTP cells
    – 64-bit unique device number
■ Common Flash Interface (CFI)
■ 100 000 program/erase cycles per block

PSRAM
■ Access time: 70 ns
■ Asynchronous Page Read
    – Page size: 8 words
    – First access within page: 70 ns
    – Subsequent read within page: 20 ns
■ Three Power-down modes
    – Deep Power-Down
    – Partial Array Refresh of 4 Mbits
    – Partial Array Refresh of 8 Mbits

Intel’s Word-Wide FlashFile™ MEMORY family provides high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. The word-wide memories are available at various densities in the same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and MEMORY cards. Enhanced suspend capabilities provide an ideal solution for code or data storage applications.

■ Two 32-Byte Write Buffers
    - 2 µs per Byte Effective Programming Time
■ Operating Voltage
    - 5V VCC
    - 5V VPP
■ 70 ns Read Access Time (16 Mbit) 90 ns Read Access Time (32 Mbit)
■ High-Density Symmetrically-Blocked Architecture
    - 32 64-Kbyte Erase Blocks (16 Mbit)
    - 64 64-Kbyte Erase Blocks (32 Mbit)
■ System Performance Enhancements
    - STS Status Output
■ Industry-Standard Packaging
    - SSOP and TSOP (16 Mbit)
    - SSOP (32 Mbit)
■ Cross-Compatible Command Support
    - Intel Standard Command Set
    - Common Flash Interface (CFI)
    - Scaleable Command Set (SCS)
■ 100,000 Block Erase Cycles
■ Enhanced Data Protection Features
    - Absolute Protection with VPP = GND
    - Flexible Block Locking
    - Block Erase/Program Lockout during Power Transitions
■ Configurable x8 or x16 I/O
■ Automation Suspend Options
    - Program Suspend to Read
    - Block Erase Suspend to Program
    - Block Erase Suspend to Read
■ ETOX™ V Nonvolatile Flash Technology

Intel’s 28F016SV 16-Mbit FlashFile™ MEMORY is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash MEMORY systems. With innovative capabilities, low-power operation, user-selectable VPP voltage and high read/program performance, the 28F016SV enables the design of truly mobile, high-performance personal computing and communications products.

SmartVoltage Technology

  - User-Selectable 3.3V or 5V VCC

  - User-Selectable 5V or 12V VPP

65 ns Access Time

1 Million Erase Cycles per Block

30.8 MB/sec Burst Write Transfer Rate

0.48 MB/sec Sustainable Write Transfer Rate

Configurable x8 or x16 Operation

56-Lead TSOP and SSOP Type I Packages

Backwards-Compatible with 28F016SA, 28F008SA Command Set

Revolutionary Architecture

  - Multiple Command Execution

  - Program during Erase

  - Command Super-Set of the Intel 28F008SA

  - Page Buffer Program

2 µA Typical Deep Power-Down

32 Independently Lockable Blocks

State-of-the-Art 0.6 µm ETOX™ IV Flash Technology

DESCRIPTION
The M36DR432 is a multichip MEMORY device containing a 32 Mbit boot block Flash MEMORY and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package.
The two components are distinguished by use with three chip enable inputs: EF for the Flash MEMORY and, E1S and E2S for the SRAM. The two components are also separately power supplied and grounded.

FEATURES SUMMARY
■ SUPPLY VOLTAGE
    – VDDF = VDDS =1.9V to 2.1V
    – VPPF = 12V for Fast Program (optional)
■ ACCESS TIME: 85,100ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
    – Manufacturer Code: 20h
    – Top Device Code, M36DR432C: 00A4h
    – Bottom Device Code, M36DR432D: 00A5h

FLASH MEMORY
■ 32 Mbit (2Mb x16) BOOT BLOCK
    – Parameter Blocks (Top or Bottom Location)
■ PROGRAMMING TIME
    – 10µs typical
    – Double Word Programming Option
■ ASYNCRONOUS PAGE MODE READ
    – Page width: 4 Word
    – Page Mode Access Time: 35ns
■ DUAL BANK OPERATION
    – Read within one Bank while Program or Erase within the other
    – No Delay between Read and Write Operations
■ BLOCK PROTECTION ON ALL BLOCKS
    – WPF for Block Locking
■ COMMON FLASH INTERFACE
    – 64 bit Security Code

SRAM
■ 4 Mbit (256K x 16 bit)
■ LOW VDDS DATA RETENTION: 1V
■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS

SUMMARY DESCRIPTION

The M36W216TI is a low voltage Multiple MEMORY Product which combines two MEMORY devices; a

16 Mbit boot block Flash MEMORY and a 2 Mbit SRAM. Recommended operating conditions do not allow both the Flash MEMORY and the SRAM MEMORY to be active at the same time. The MEMORY is offered in a Stacked LFBGA66 (12x8mm, 8 x 8 active ball, 0.8 mm pitch) package and is supplied with all the bits erased (set to ‘1’).

FEATURES SUMMARY

■MULTIPLE MEMORY PRODUCT

– 16 Mbit (1Mb x 16) Boot Block Flash MEMORY

– 2 Mbit (128Kb x 16) SRAM

■SUPPLY VOLTAGE

–VDDF= VDDS= 2.7V to 3.3V

–VDDQF= VDDS= 2.7V to 3.3V

–VPPF= 12V for Fast Program (optional)

■ACCESS TIME: 70ns, 85ns

■LOW POWER CONSUMPTION

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M36W216TI: 88CEh

– Bottom Device Code, M36W216BI: 88CFh