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Part Name(s) : LPC1763FBD100 LPC1764FBD100 LPC1765FBD100 LPC1765FET100 LPC1766FBD100 LPC1767FBD100 LPC1768FBD100 LPC1768FET100 LPC1768UK LPC1769FBD100 NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN View

Features and benefits

* ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1768/67/66/65/64/63) or ofup to 120 MHz (LPC1769). A Memory Protection Unit

(MPU) supporting eight regions is included.

* ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

* up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator

enables high-speed 120 MHz operation with zero wait states.

* In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.

* On-chip SRAM includes:

* 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU

access.


Part Name(s) : LPC1774FBD144 LPC1774FBD208 LPC1776FBD208 LPC1776FET180 LPC1777FBD208 LPC1778FBD144 LPC1778FBD208 LPC1778FET180 LPC1778FET208 LPC177X NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 6 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC View

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.



The ARM Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals.



The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches.

The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x operates at up to 120 MHz CPU frequency.


Part Name(s) : LPC1311FHN33 LPC1311FHN33/01 LPC1313FBD48 LPC1313FBD48/01 LPC1313FHN33 LPC1313FHN33/01 LPC1342FBD48 LPC1342FHN33 LPC1343FBD48 LPC1343FHN33 NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device View

 General description

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.



 


Part Name(s) : LPC1315FBD48 LPC1315FHN33 LPC1316FBD48 LPC1316FHN33 LPC1317FBD48 LPC1317FBD64 LPC1317FHN33 LPC1345FBD48 LPC1345FHN33 LPC1346FBD48 NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM View

General description
The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.

Features and benefits
 System:
  ARM Cortex-M3 r2p1 processor, running at frequencies of up to 72 MHz.
  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
  Non Maskable Interrupt (NMI) input selectable from several input sources.
  System tick timer.
 Memory:
  up to 64 kB on-chip flash program memory with a 256 byte page erase function.
  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash updates via USB supported.
  up to 4 kB on-chip EEPROM data memory with on-chip API support.
  up to 12 kB SRAM data memory.
  16 kB boot ROM with API support for USB API, power control, EEPROM, and flash IAP/ISP.
 Debug options:
  Standard JTAG test interface for BSDL.
  Serial Wire Debug.
  Support for ETM ARM Cortex-M3 debug time stamping.
 Digital peripherals:
  up to 51 General Purpose I/O (GPIO) pins with configurablepull-up/pull-down resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins support programmable glitch filter.
  up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
  Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
  High-current source output driver (20 mA) on one pin (P0_7).
  High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
  Four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs.
  Programmable Windowed WatchDog Timer (WWDT) with a internal low-power WatchDog Oscillator (WDO).
  Repetitive Interrupt Timer (RI Timer).
 Analog peripherals:
  12-bit ADC with eight input channels and sampling rates of up to 500 kSamples/s. 
   Serial interfaces:
  USB 2.0 full-speed device controller (LPC1345/46/47) with on-chip ROM-based USB driver library.
  USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3).
  Two SSP controllers with FIFO and multi-protocol capabilities.
  I2C-bus interface supporting the full I2C-bus specification andFast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
 Clock generation:
  Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator) with failure detector.
  12 MHz high-frequency Internal RC oscillator (IRC) trimmed to 1 % accuracy over the entire voltage and temperature range. The IRC can optionally be used as a system clock.
  Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output.
  PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.
  A second, dedicated PLL is provided for USB (LPC1345/46/47).
  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.
 Power control:
  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
  Power profiles residing in boot ROM allow optimized performance and minimized power consumption for any given application through one simple function call.
  Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity.
  Processor wake-up from Deep power-down mode using one special function pin.
  Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes.
  Power-On Reset (POR).
  Brownout detect with up to four separate thresholds for interrupt and forced reset.
 Unique device serial number for identification.
 Single 3.3 V power supply (2.0 V to 3.6 V).
 Temperature range 40 C to +85 C.
 Available as LQFP64, LQFP48, and HVQFN33 package.

 Applications
 Consumer
    peripherals  
    Handheld scanners
 Medical
 USB audio devices
 Industrial control


Part Name(s) : LPC1751 LPC1752 LPC1754 LPC1756 LPC1758 LPC1759 LPC1759FBD80 LPC1758FBD80 LPC1756FBD80 LPC1754FBD80 Philips
Philips Electronics
Description : 32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN View

General description

The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 2 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 6 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 52 general purpose I/O pins.



Features

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit (MPU) supporting eight regions is included.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.

■ In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.

■ On-chip SRAM includes:

   ♦ up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.

   ♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.

      These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.

■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.

■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

   AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.

■ Split APB bus allows high throughput with few stalls between the CPU and DMA.

■ Serial interfaces:

   ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.

   ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.

   ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.

   ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.

   ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.

   ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.

   ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kBit/s with multiple address recognition and monitor mode.

   ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.

■ Other peripherals:

   ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.

   ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.

   ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.

   ♦ Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.

   ♦ One motor control PWM with support for three-phase motor control.

   ♦ Quadrature encoder interface that can monitor one external quadrature encoder.

   ♦ One standard PWM/timer block with external count input.

   ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.

   ♦ Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.

   ♦ ARM Cortex-M3 system tick timer, including an external clock input option.

   ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.

   ♦ Each peripheral has its own clock divider for further power savings.

■ Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.

■ Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.

■ Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.

■ Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.

■ Single 3.3 V power supply (2.4 V to 3.6 V).

■ One external interrupt input configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.

■ Non-maskable Interrupt (NMI) input.

■ The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes.

■ Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt (LPC1758 only), CAN bus activity, Port 0/2 pin interrupt, and NMI).

■ Brownout detect with separate threshold for interrupt and forced reset.

■ Power-On Reset (POR).

■ Crystal oscillator with an operating range of 1 MHz to 25 MHz.

■ 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.

■ PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

■ USB PLL for added flexibility.

■ Code Read Protection (CRP) with different security levels.

■ Unique device serial number for identification purposes.

■ Available as 80-pin LQFP package (12 mm × 12 mm × 1.4 mm).



Applications

■ eMetering

■ Lighting

■ Industrial networking

■ AlARM systems

■ White goods

■ Motor control



 


Part Name(s) : LPC8N04 LPC8N04FHI24 NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex®-M0+ microcontroller; 32 kB flash and 8 kB SRAM; NFC/RFID ISO 14443 type A interf View

General description
The NXP LPC8N04 is an IC optimized for an entry level Cortex-M0+ MCU with built-in NFC interface. LPC8N04 supports an effective system solution with a minimal number of external components for NFC related applications. The embedded ARM Cortex-M0+ offers flexibility to the users of this IC to implement their own dedicated solution. The LPC8N04 contains multiple features, including multiple power-down modes and a selectable CPU frequency of up to 8 MHz, for ultra-low power consumption.

Features and benefits
■System
   ◆ARM Cortex-M0+ processor running at frequencies of up to 8 MHz
   ◆ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC)
   ◆ARM Serial Wire Debug (SWD)
   ◆System tick timer
   ◆IC reset input
■Memory
   ◆32 kB on-chip flash programming memory
   ◆4 kB on-chip EEPROM of which 256 byte can be write protected
   ◆8 kB SRAM
■Digital peripherals
   ◆up to 12 General Purpose Input Output (GPIO) pins with configurable pull-up/pull-down resistors and repeater mode
   ◆GPIO pins which can be used as edge and level sensitive interrupt sources
   ◆High-current drivers/sinks (20 mA) on four GPIO pins
   ◆High-current drivers/sinks (20 mA) on two I2C-bus pins
   ◆Programmable WatchDog Timer (WDT)
■Analog peripherals
   ◆Temperature sensor with 1.5℃ absolute temperature accuracy between 40℃ and +85℃
■Communication interfaces
   ◆NFC/RFID ISO 14443 type A interface
   ◆I2C-bus interface supporting full I2C-bus specification and fast mode with a data rate of 400 kBit/s, with multiple address recognition and monitor mode
■Energy harvesting functionality to power the LPC8N04.
■Clock generation
   ◆8 MHz internal RC oscillator, trimmed to 2 % accuracy, which is used for the system clock
   ◆Timer oscillator operating at 32 kHz linked to the RTC timer unit
■Power control
   ◆Support for 1.72 V to 3.6 V external voltages
   ◆The LPC8N04 can also be powered from the NFC field
   ◆Activation via NFC possible
   ◆Integrated Power Management Unit (PMU) for versatile control of power consumption
   ◆Four reduced power modes for ARM Cortex-M0+: sleep, deep sleep, deep power-down and battery off
   ◆Power gating for each analog peripheral for ultra-low power operation
   ◆< 50 nA IC current consumption in battery off mode at 3.0 V
   ◆Power-On Reset (POR)
■Unique device serial number for identification

Applications
■ Configurable LED strip/christmas tree LEDs via NFC
■ Smart toy/interactive robot data logger
■ Buttonless/contactless control panel
■ Contactless diagnostic
■ NFC e-locker
■ Smart manufacturing
■ NFC OTA

Part Name(s) : LPC1751FBD80 LPC1751FBD80,551 LPC1752FBD80 LPC1752FBD80,551 LPC1754FBD80 LPC1754FBD80,551 LPC1756FBD80 LPC1756FBD80/CP327 LPC1758FBD80 LPC1758FBD80Y NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN View

General description

The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.



Features and benefits

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit

   (MPU) supporting eight regions is included.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.

■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.

■ On-chip SRAM includes:

♦ up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.

♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.

■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.

 

■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.

■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.

■ Split APB bus allows high throughput with few stalls between the CPU and DMA.

■ Serial interfaces:

 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.

 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.

 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.

 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.

 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.

 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.

 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kBit/s with multiple address recognition and monitor mode.

 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.

■ Other peripherals:

 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.

 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.

 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.

 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.

 ♦ One motor control PWM with support for three-phase motor control.

 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.

 ♦ One standard PWM/timer block with external count input.

 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.

 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.

 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.

 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.

    ♦ Each peripheral has its own clock divider for further power savings.



 


Part Name(s) : LBGA256 LPC1810 LPC1810FBD144 LPC1810FET100 LPC1820 LPC1820FBD144 LPC1820FET100 LPC1830 LPC1830FBD144 LPC1830FET100 NXP
NXP Semiconductors.
Description : 32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller View

General description
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC1850/30/20/10 operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.

Features and benefits
■ Processor core
   ◆ ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.
   ◆ ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
   ◆ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
   ◆ Non-maskable Interrupt (NMI) input.
   ◆ JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
   ◆ Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
   ◆ System tick timer.
■ On-chip memory
   ◆ 200 kB SRAM for code and data use.
   ◆ Multiple SRAM blocks with separate bus access.
   ◆ 64 kB ROM containing boot code and on-chip software drivers.
   ◆ 32-bit One-Time Programmable (OTP) memory for general-purpose use.
■ Clock generation unit
   ◆ Crystal oscillator with an operating range of 1 MHz to 25 MHz.
   ◆ 12 MHz internal RC oscillator trimmed to 1 % accuracy over temperature and
      voltage.
   ◆ Ultra-low power RTC crystal oscillator.
   ◆ Three PLLs allow CPU operation up to the maximum CPU rate without the need for
      a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
      third PLL can be used as audio PLL.
   ◆ Clock output.
■ Configurable digital peripherals:
   ◆ State Configurable Timer (SCT) subsystem on AHB.
   ◆ Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
      outputs to event driven peripherals like timers, SCT, and ADC0/1.
■ Serial interfaces:
   ◆ Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to
      52 MB per second.
   ◆ 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
      throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
      stamping (IEEE 1588-2008 v2).
   ◆ One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
      on-chip high-speed PHY (USB0).
   ◆ One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
      full-speed PHY and ULPI interface to an external high-speed PHY (USB1).
   ◆ USB interface electrical test software included in ROM USB stack.
   ◆ Four 550 UARTs with DMA support: one UART with full modem interface; one
      UART with IrDA interface; three USARTs support UART synchronous mode and a
      smart card interface conforming to ISO7816 specification.
   ◆ up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
      excludes operation of all other peripherals connected to the same bus bridge See
      Figure 1 and Ref. 1.
   ◆ Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
      support.
   ◆ One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
      pins conforming to the full I2C-bus specification. Supports data rates of up to
      1 Mbit/s.
   ◆ One standard I2C-bus interface with monitor mode and standard I/O pins.
   ◆ Two I2S interfaces with DMA support, each with one input and one output. (Continue ...)

Part Name(s) : HT32F1251 HT32F1251B HT32F1252 HT32F1253 Holtek
Holtek Semiconductor
Description : Holtek 32-bit Microcontroller with ARM®Cortex™-M3 Core View

General Description

The Holtek HT32F125x series of devicesare high performance, low power consumption 32-bit microcontrollers based ontheARM® Cortex™-M3 processor core. The Cortex™-M3 is a next generation processor core which is tightly coupled withaNested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.



 


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