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Part Name(s) : CY7C1325G-117BGC CY7C1325G-117BGI CY7C1325G-117BGXC CY7C1325G-117BGXI CY7C1325G-117AXC CY7C1325G-117AXI Cypress
Cypress Semiconductor
Description : 4-Mbit (256K x 18) Flow-Through Sync SRAM View

Functional Description[1]
The CY7C1325G is a 262,144 x 18 Synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
256K X 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
    — 7.5 ns (117-MHz version)
    — 8.0 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
Synchronous self-timed write
• ASynchronous output enable
• Lead-Free 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode option

Part Name(s) : CY7C1353G CY7C1353G-133AXC CY7C1353G-133AXI CY7C1353G-100AXC CY7C1353G-100AXI CY7C1353G CY7C1353G-133AXC CY7C1353G-133AXI CY7C1353G-117AXC CY7C1353G-117AXI Cypress
Cypress Semiconductor
Description : 4-Mbit (256K x 18) Flow-Through SRAM with NoBL™ Architecture View

Functional Description[1]
The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

Features
• Supports up to 133-MHz bus operations with zero wait states
    — Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
256K x 18 common IO architecture
• 2.5V/3.3V IO power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
Synchronous self timed writes
• ASynchronous Output Enable
• Available in Pb-free 100-Pin TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power

Part Name(s) : CY7C1361C-133BZXI CY7C1361C-133BGXC CY7C1361C-100BGXI CY7C1361C-133BGXI CY7C1361C-100BZXC CY7C1361C-100BZXI CY7C1361C-133BZXC CY7C1361C-100BGXC CY7C1361C-100AXE Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM View

Functional Description[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-Through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• Supports 100, 133-MHz bus operations
• Supports 100-MHz bus operations (Automotive)
256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
Synchronous self-timed write
• ASynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option

Part Name(s) : CY7C1353F CY7C1353F-133AC CY7C1353F-133AI CY7C1353F-117AC CY7C1353F-117AI CY7C1353F-100AC CY7C1353F-100AI CY7C1353F-66AC CY7C1353F-66AI Cypress
Cypress Semiconductor
Description : 4-Mb (256K x 18) Flow-Through SRAM with NoBL™ Architecture View

Functional Description[1]
The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

Features
• Can support up to 133-MHz bus operations with zero wait states
    — Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
256K x 18 common I/O architecture
• 2.5V / 3.3V I/O power supply
• Fast clock-to-output times
    — 6.5 ns (for 133-MHz device)
    — 7.5 ns (for 117-MHz device)
    — 8.0 ns (for 100-MHz device)
    — 11.0 ns (for 66-MHz device)
• Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
• ASynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power


Part Name(s) : CY7C1297F CY7C1297F-117AC Cypress
Cypress Semiconductor
Description : 1-Mbit (64K x 18) Flow-Through Sync SRAM View

Functional Description[1]
The CY7C1297F is a 131,072 x 18 Synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• 64K x 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
    — 7.5 ns (117-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
Synchronous self-timed write
• ASynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard 100-pin TQFP
• “ZZ” Sleep Mode option

Part Name(s) : CY7C1297H CY7C1297H-100AXC CY7C1297H-100AXI CY7C1297H-133AXC CY7C1297H-133AXI Cypress
Cypress Semiconductor
Description : 1-Mbit (64K x 18) Flow-Through Sync SRAM View

Functional Description[1]
The CY7C1297H is a 64K x 18 Synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• 64K x 18 common I/O
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (for 133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
Synchronous self-timed write
• ASynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP package
• “ZZ” Sleep Mode option

Part Name(s) : CY7C1362C-166BGI CY7C1362C-166BGXI CY7C1362C-166BZI Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Pipelined SRAM View

Functional Description[1]
The CY7C1360C/CY7C1362C SRAM integrates 256K x 36 and 512K x 18 SRAM cells with advanced Synchronous peripheral circuitry and a two-bit counter for internal burst operation.

Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O operation (VDDQ)
• Fast clock-to-output times
    — 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
Synchronous self-timed writes
• ASynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan

Part Name(s) : M36DR432-ZAT M36DR432A M36DR432A100ZA6C M36DR432A100ZA6T M36DR432A120ZA6C M36DR432A120ZA6T M36DR432AZA M36DR432B M36DR432B100ZA6C M36DR432B100ZA6T STMICROELECTRONICS
STMicroelectronics
Description : 32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 4 Mbit (256K x16) SRAM, Multiple Memory Product View

DESCRIPTION
The M36DR432 is a multichip memory device containing a 32 Mbit boot block Flash memory and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package.

FEATURES SUMMARY
■ SUPPLY VOLTAGE
    – VDDF = VDDS =1.65V to 2.2V
    – VPPF = 12V for Fast Program (optional)
■ ACCESS TIME: 100,120ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
    – Manufacturer Code: 20h
    – Top Device Code, M36DR432A: 00A0h
    – Bottom Device Code, M36DR432B: 00A1h

FLASH MEMORY
■ 32 Mbit (2Mb x16) BOOT BLOCK
    – Parameter Blocks (Top or Bottom Location)
■ PROGRAMMING TIME
    – 10µs typical
    – Double Word Programming Option
■ ASyncRONOUS PAGE MODE READ
    – Page width: 4 Word
    – Page Mode Access Time: 35ns
■ DUAL BANK OPERATION
    – Read within one Bank while Program or Erase within the other
    – No Delay between Read and Write Operations
■ BLOCK PROTECTION ON ALL BLOCKS
    – WPF for Block Locking
■ COMMON FLASH INTERFACE
    – 64 bit Security Code

SRAM
■ 4 Mbit (256K x 16 bit)
■ LOW VDDS DATA RETENTION: 1V
■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS

Part Name(s) : CY7C1355C-100AC CY7C1355C-100AI CY7C1355C-117AC CY7C1355C-117AI CY7C1355C-117BGC CY7C1355C-117BGI CY7C1355C-117BZC CY7C1355C-117BZI CY7C1355C-133AC CY7C1355C-133AI Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture View

Functional Description[1]
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

Features
• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero wait states
    — Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
    — 6.5 ns (for 133-MHz device)
    — 7.0 ns (for 117-MHz device)
    — 7.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
• ASynchronous Output Enable
• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and 165-Ball fBGA packages
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ mode or CE deselect
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power

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