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Description : PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated FIRST-IN, FIRST-OUT memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side MEMORY arrays for data transfers in two directions.
   
FEATURES:
• Two side-by-side FIFO MEMORY arrays for BIDIRECTIONAL
    data transfers
512 x 18-Bit - 512 x 18-Bit (IDT72511)
• 1024 x 18-Bit - 1024 x 18-Bit (IDT72521)
• 18-bit data buses on Port A side and Port B side
• Can be configured for 18-to-18-bit or 36-to-36-bit communication
• Fast 35ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
    ports
• Two fixed flags, Empty and Full, for both the A-to-B and
    the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
    for each FIFO
• Programmable flag offset can be set to any depth in the
    FIFO
• Any of the eight flags can be assigned to four external
    flag pins
• Flexible reread/rewrite capabilities
• Six general-purpose programmable I/O pins
• Standard DMA control pins for data exchange with
    peripherals
• 68-pin PGA and PLCC packages
   

Elpida
Elpida Memory, Inc
Description : 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 133 MHz MEMORY Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC133SDRAM

Description
The HB52F649E1 belongs to 8-byte DIMM (Dual In-line MEMORY Module) family, and has been developed as an optimized main MEMORY solution for 8-byte processor applications. The HB52F649E1 is a 64M × 72 × 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 3 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52F649E1 is 168-pin socket type package (dual lead out). Therefore, the HB52F649E1 makes high density mounting possible without surface mount technology. The HB52F649E1 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
• 168-pin socket type package (dual lead out)
    - Outline: 133.35 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 133 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 4 (133 MHz) : 3 (100 MHz)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

Description : CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high-speed, low-power FIRST-IN, FIRST-OUT (FIFO) memories with clocked read and write controls.
   
FEATURES:
• 256 x 18-bit organization array (IDT72205LB)
512 x 18-bit organization array (IDT72215LB)
• 1,024 x 18-bit organization array (IDT72225LB)
• 2,048 x 18-bit organization array (IDT72235LB)
• 4,096 x 18-bit organization array (IDT72245LB)
• 10 ns read/write cycle time
• Empty and Full flags signal FIFO status
• Easily expandable in depth and width
• Asynchronous or coincident read and write clocks
• Programmable Almost-Empty and Almost-Full flags with
    default settings
• Half-Full flag capability
• Dual-Port zero fall-through time architecture
• Output enable puts output data bus in high-impedance
    state
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)
    and plastic leaded chip carrier (PLCC)
• Industrial temperature range (–40°C to +85°C) is available
   

ST-Microelectronics
STMicroelectronics
Description : 512 Kbit, Low Voltage, Serial Flash MEMORY With 20 MHz SPI Bus Interface

SUMMARY DESCRIPTION
The M25P05 is a 512 Kbit (64K x 8) Serial Flash MEMORY, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The MEMORY can be programmed 1 to 128 bytes at a time, using the Page Program instruction.
The MEMORY is organized as 2 sectors, each containing 256 pages. Each page is 128 bytes wide.
Thus, the whole MEMORY can be viewed as consisting of 512 pages, or 65536 bytes.
The whole MEMORY can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES SUMMARY
This device is now designated as “Not for New Design”. Please use the M25P05-A in all future designs (as described in application note AN1511).
512 Kbit of Flash MEMORY
■ Page Program (up to 128 Bytes) in 3 ms (typical)
■ Sector Erase (256 Kbit) in 1 s (typical)
■ Bulk Erase (512 Kbit) in 2 s (typical)
■ 2.7 V to 3.6 V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 20 MHz Clock Rate (maximum)
■ Deep Power-down Mode 1 µA (typical)
■ Electronic Signature
■ More than 100,000 Erase/Program Cycles per Sector
■ More than 20 Year Data Retention

Elpida
Elpida Memory, Inc
Description : 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz MEMORY Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line MEMORY Module) family, and has been developed as an optimized main MEMORY solution for 8-byte processor applications. The HB52E649E12 is a 64M × 72 × 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin socket type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible without surface mount technology. The HB52E649E12 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev.1.2)
• 168-pin socket type package (dual lead out)
    - Outline: 133.37 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 3/4 (HB52E649E12-A6B) : 4 (HB52E649E12-B6B)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

SLS
System Logic Semiconductor
Description : STROBED Hex Inverter/Buffer

STROBED Hex Inverter/Buffer
High-Voltage Silicon-Gate CMOS

The SL4502B consists of six inverter/buffers with 3-state outputs. A logic “1” on the OUTPUT ENABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A logic “1” on the DIRECTION input switches all six outputs to logic “0” if the OUTPUT ENABLE input is a logic “0”.

 • Operating Voltage Range: 3.0 to 18 V
 • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
 • Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

System-Logic
System Logic Semiconductor
Description : STROBED Hex Inverter/Buffer High-Voltage Silicon-Gate CMOS

STROBED Hex Inverter/Buffer High-Voltage Silicon-Gate CMOS

The SL4502B consists of six inverter/buffers with 3-state outputs. A logic “1” on the OUTPUT ENABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A logic “1” on the DIRECTION input switches all six outputs to logic “0” if the OUTPUT ENABLE input is a logic “0”.

 • Operating Voltage Range: 3.0 to 18 V
 • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
 • Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

Motorola
Motorola => Freescale
Description : STROBED Hex Inverter / Buffer

STROBED Hex Inverter / Buffer



The MC14502B is aSTROBED hex buffer/inverter with 3–state outputs, an inhibit control, and guaranteed TTL drive over the temperature range. The 3–state output simplifies design by allowing a common bus.



• Separate Output Disable Control

• 3–State Output

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving 4LSTTL Loads Over the Rated Temperature Range

 


Description : CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2

DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power BIDIRECTIONAL FIRST-IN, FIRST-OUT (FIFO) memories, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO MEMORY arrays are contained in the SyncBiFIFO; one data buffer for each direction.
   
FEATURES:
• Two independent FIFO memories for fully BIDIRECTIONAL data
    transfers
• 256 x 18 x 2 organization (IDT72605)
512 x 18 x 2 organization (IDT72615)
• Synchronous interface for fast (20ns) read and write cycle times
• Each data port has an independent clock and read/write control
• Output enable is provided on each port as a three-state control
    of the data bus
• Built-in bypass path for direct data transfer between two ports
• Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO
• Programmable flag offset can be set to any depth in the FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
    Quad Flatpack) and 68-pin PLCC
• Industrial temperature range (–40°C to +85°C)
• Green parts available, see ordering information
   

Part Name(s) : MC-4R512FKE8D-840
Elpida
Elpida Memory, Inc
Description : Direct Rambus DRAM RIMM™ Module 512M-BYTE (256M-WORD x 18-BIT)

Description
The Direct Rambus RIMM module is a general-purpose high-performance MEMORY module subsystem suitable for use in a broad range of applications including computer MEMORY, personal computers, workstations, and other applications where high bandwidth and low latency are required.
MC-4R512FKE8D modules consists of sixteen 288M Direct Rambus DRAM (Direct RDRAM) devices (µPD488588). These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and board design technologies.

Features
• 184 edge connector pads with 1mm pad spacing
512 MB Direct RDRAM storage
• Each RDRAM® has 32 banks, for 512 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
• Over Drive Factor (ODF) support

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