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Part Name(s) : GS880E32BT-225 GS880E32BT-225I GSI
Giga Semiconductor
Description : 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs View

Functional Description
Applications
The GS880E18/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available

Part Name(s) : GS816118D GS816118D-133 GS816118D-133I GS816118 GS816118D-150 GS816118D-150I GS816118D-166 GS816118D-166I GS816118D-200 GS816118D-200I ETC1
Unspecified
Description : 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs View

[GSI]

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Part Name(s) : GS832218 GS832236C-133 GS832236C-133I GSI
Giga Semiconductor
Description : 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs View

2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs



Features

• FTpin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBOpin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package



Functional Description

Applications

The GS832218/36/72 is a 37,748,736-bit high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from

DSP main store to networking chip set support.



 


Part Name(s) : GS816118D-133 GS816118D-133I GS816118D-150 GS816118D-150I GS816118D-166 GS816118D-166I GS816118D-200 GS816118D-200I GS816118D-225 GS816118D-225I GSI
Giga Semiconductor
Description : 1M x 18, 512K x 36 18Mb Sync Burst SRAMs View

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs


Part Name(s) : GS88236BD-333 GS88236BD-300 GS88218BD-333I GS88218BD-300I GS88236BD-333I GS88236BD-300I GSI
Giga Semiconductor
Description : 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs View

Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages

Part Name(s) : CY7C1361C-133BZXI CY7C1361C-133BGXC CY7C1361C-100BGXI CY7C1361C-133BGXI CY7C1361C-100BZXC CY7C1361C-100BZXI CY7C1361C-133BZXC CY7C1361C-100BGXC CY7C1361C-100AXE Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM View

Functional Description[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a Burst and increments the address automatically for the rest of the Burst access.

Features
• Supports 100, 133-MHz bus operations
• Supports 100-MHz bus operations (Automotive)
256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable Burst counter supporting Intel® Pentium® interleaved or linear Burst sequences
• Separate processor and controller address strobes
Synchronous self-timed write
• ASynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option

Part Name(s) : GS88218BB-333 GS88218BB-300 GS88236BB-333 GS88236BB-300 GS88218BB-333I GS88218BB-3005I GS88236BB-333I GS88236BB-300I GS88218BD-333 GS88218BD-300 GSI
Giga Semiconductor
Description : 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs View

Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages

Part Name(s) : GS88032BT-133I GS88036BT-133I GS88036BT-166I GS88036BT-225I GS880E32BT-133 GS880E32BT-133I GS88018BT-225 GS88018BT-166 GS88018BT-133 GS88032BT-225 GSI
Giga Semiconductor
Description : 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs View

Functional Description
Applications
The GS88018/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.
   
Features
• FT pin for user-configurable flow through or pipeline operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
   

Part Name(s) : A67L8316E-45 A67L8316E-6 AMICC
AMIC Technology
Description : 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM View

General Description
The AMIC Direct Bus Alternation™ (DBA™ ) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8316, A67L8318, A67L7332, A67L7336 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced Synchronous peripheral circuitry and a 2-bit Burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write Read alternation. The positive edge triggered single clock input (CLK) controls all Synchronous inputs passing through the registers.

Features
● Fast access time: 4.0/4.2/4.5/5.0 ns (143,133,117,100MHz)
● Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization
● Signal +3.3V ±5% power supply
● Individual Byte Write control capability
● Clock enable (CEN) pin to enable clock and suspend operations
● Clock-controlled and registered address, data and control signals
● Registered output for pipelined applications
● Three separate chip enables allow wide range of options for CE control, address pipelining
● Internally self-timed write cycle
● Selectable Burst mode (Linear or Interleaved)
● SLEEP mode (ZZ pin) provided
● Available in 100 pin LQFP package

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