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GSI
Giga Semiconductor
Description : 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

Functional Description
Applications
The GS880E18/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available

GSI
Giga Semiconductor
Description : 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs



Features

• FTpin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBOpin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package



Functional Description

Applications

The GS832218/36/72 is a 37,748,736-bit high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from

DSP main store to networking chip set support.



 


Description : 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

[GSI]

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Description : 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages

Description : 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Functional Description[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a Burst and increments the address automatically for the rest of the Burst access.

Features
• Supports 100, 133-MHz bus operations
• Supports 100-MHz bus operations (Automotive)
256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable Burst counter supporting Intel® Pentium® interleaved or linear Burst sequences
• Separate processor and controller address strobes
Synchronous self-timed write
• ASynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option

Description : 512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION
The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256K x 32.

FEATURES
■ Fast clock speed: 166, 150, 133, and 100MHz
■ Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
■ Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
■ Single +2.5V ± 5% power supply (VCC)
■ Snooze Mode for reduced-standby power
■ Individual Byte Write control
■ Clock-controlled and registered addresses, data I/Os and control signals
Burst control (interleaved or linear Burst)
■ Packaging:
    ■ 209-bump BGA package
■ Low capacitive bus loading

Description : 1M x 18, 512K x 36 18Mb Sync Burst SRAMs

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GSI
Giga Semiconductor
Description : 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Features

• FT pin for user-configurable flow through or pipeline operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package



 


Description : 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages

Description : 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

Functional Description
Applications
The GS880F18/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance Synchronous SRAM with a 2-bit Burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in Synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package

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