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Part Name(s) : SL74HC595D SL74HC595N SL74HC595 System-Logic
System Logic Semiconductor
Description : or="FF003B">8-Bit or="FF003B">Serial-Input/or="FF003B">Serial or Parallel-Output Shift Register with Latched 3-State Outputs View

or="FF003B">8-Bit or="FF003B">Serial-Input/or="FF003B">Serial or Parallel-Output Shift Register with Latched 3-State Outputs
High-Performance Silicon-Gate CMOS

The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC595 consists of an or="FF003B">8-Bit Shift Register and an or="FF003B">8-Bit D-type latch with three-state parallel outputs. The Shift Register accepts or="FF003B">Serial data and provides a or="FF003B">Serial output. The Shift Register also provides parallel data to the or="FF003B">8-Bit latch. The Shift Register and latch have independent clock inputs. This device also has an asynchronous reset for the Shift Register.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : HC595 SL74HC595 SL74HC595N SL74HC595D SLS
System Logic Semiconductor
Description : or="FF003B">8-Bit or="FF003B">Serial-Input/or="FF003B">Serial or Parallel-Output Shift Register with Latched 3-State Outputs View

or="FF003B">8-Bit or="FF003B">Serial-Input/or="FF003B">Serial or Parallel-Output Shift Register with Latched 3-State Outputs
High-Performance Silicon-Gate CMOS

The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC595 consists of an or="FF003B">8-Bit Shift Register and an or="FF003B">8-Bit D-type latch with three-state parallel outputs. The Shift Register accepts or="FF003B">Serial data and provides a or="FF003B">Serial output. The Shift Register also provides parallel data to the or="FF003B">8-Bit latch. The Shift Register and latch have independent clock inputs. This device also has an asynchronous reset for the Shift Register.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : SL74HC165 SL74HC165D SL74HC165N HC165 SLS
System Logic Semiconductor
Description : or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/or="FF003B">Serial-Output Shift Register View

or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/or="FF003B">Serial-Output Shift Register
High-Performance Silicon-Gate CMOS

The SL74HC165 is identical in pinout to the LS/ALS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is an or="FF003B">8-Bit Shift Register with complementary outputs from the last stage. Data may be loaded into the Register either in parallel or in or="FF003B">Serial form. When the or="FF003B">Serial Shift/ Parallel Load input is low, the data is loaded asynchronously in parallel. When the or="FF003B">Serial Shift/Parallel Load input is high, the data is loaded or="FF003B">Serially on the rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input Nor clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : MC54HC165A MC54HC165AJ MC74HC165AN MC74HC165AD MC74HC165ADT MC74HC165A Motorola
Motorola => Freescale
Description : or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/or="FF003B">Serial-Output Shift Register View

8-Bit Serial or Parallel-Input/Serial-Output Shift Register
High–Performance Silicon–Gate CMOS

The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device is an 8–bit Shift Register with complementary outputs from the last stage. Data may be loaded into the Register either in parallel or in Serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded Serially on the rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2–input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates


Part Name(s) : 74F673A 74F673APC 74F673ASC 74F673ASCX 74F673ASPC Fairchild
Fairchild Semiconductor
Description : 16-Bit or="FF003B">Serial-In, or="FF003B">Serial/Parallel-Out Shift Register View

General Description
The 74F673A contains a 16-bit or="FF003B">Serial-in, or="FF003B">Serial-out Shift Register and a 16-bit Parallel-Out storage Register. A single pin serves either as an input for or="FF003B">Serial entry or as a 3-STATE or="FF003B">Serial output. In the or="FF003B">Serial-Out mode, the data recirculates in the Shift Register.
   
Features
or="FF003B">Serial-to-parallel converter
■ 16-bit or="FF003B">Serial I/O Shift Register
■ 16-bit parallel-out storage Register
■ Recirculating or="FF003B">Serial Shifting
■ Recirculating parallel transfer
■ Common or="FF003B">Serial data I/O pin
■ Slim 24 lead package
   

Part Name(s) : IN74HC595A IN74HC595AD IN74HC595AN IKSEMICON
IK Semicon Co., Ltd
Description : or="FF003B">8-Bit or="FF003B">Serial-Input/or="FF003B">Serial or Parallel-Output Shift Register with Latched 3-State Outputs High-Performance Silicon-Gate CMOS View

The IN74HC595A is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC595A consists of an or="FF003B">8-Bit Shift Register and an or="FF003B">8-Bit D type latch with three-state parallel outputs. The Shift Register accepts or="FF003B">Serial data and provides a or="FF003B">Serial output. The Shift Register also provides parallel data to the or="FF003B">8-Bit latch. The Shift Register and latch have independent clock inputs. This device also has an asynchronous reset for the Shift Register.



• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices


Part Name(s) : MC74HC165ADT MC74HC165AFL1 MC74HC165AFL2 MC74HC165AFR1 MC74HC165AFR2 MC74HC165A_00 MC74HC165AN_00 MC74HC165AD_00 MC74HC165ADR2_00 MC74HC165ADTR2_00 ON-Semiconductor
ON Semiconductor
Description : or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input or="FF003B">Serial-Output Shift Register View

8-Bit Serial or Parallel-Input/Serial-Output Shift Register
High–Performance Silicon–Gate CMOS

The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device is an 8–bit Shift Register with complementary outputs from the last stage. Data may be loaded into the Register either in parallel or in Serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded Serially on the rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2–input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

Part Name(s) : IN74HC166 IN74HC166D IN74HC166N INTE-ElectronicGRAL
Integral Corp.
Description : or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/ or="FF003B">Serial-Output Shift Register View

or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/or="FF003B">Serial-Output Shift Register
High-Performance Silicon-Gate CMOS

The IN74HC166 is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or or="FF003B">Serial-in, or="FF003B">Serial-out Shift Register with gated clock inputs and an overriding clear input. The Shift/load input establishes the parallel-in or or="FF003B">Serial-in mode. When high, this input enables the or="FF003B">Serial data input and couples the eight flip-flops for or="FF003B">Serial Shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. or="FF003B">Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive Nor gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the Register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip-flop to zero.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : IN74HC166A IN74HC166AN IN74HC166AD IKSEMICON
IK Semicon Co., Ltd
Description : or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/or="FF003B">Serial-Output Shift Register View

or="FF003B">8-Bit or="FF003B">Serial or Parallel-Input/or="FF003B">Serial-Output Shift Register
High-Performance Silicon-Gate CMOS

The IN74HC166A is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or or="FF003B">Serial-in, or="FF003B">Serial-out Shift Register with gated clock inputs and an overriding clear input. The Shift/load input establishes the parallel-in or or="FF003B">Serial-in mode. When high, this input enables the or="FF003B">Serial data input and couples the eight flip-flops for or="FF003B">Serial Shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. or="FF003B">Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive Nor gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the Register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip-flop to zero.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

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