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Part Name(s) : HM62G36256 HM62G36256BP-4 HM62G36256BP-5 Hitachi
Hitachi -> Renesas Electronics
Description : 8M Synchronous Fast Static RAM (256k-word × 36-bit) View

Description
The HM62G36256 is a Synchronous Fast Static RAM organized as 256-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA.

Features
• Power supply: 3.3 V +10%, –5%
• Clock frequency: 200 MHz to 250 MHz
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• ProgRAMmable impedance output drivers
• User selective input trip-point
• Differential, HSTL clock inputs
• ASynchronous G output control
• ASynchronous sleep mode
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single clock register-register mode

Part Name(s) : MCM63Z736 MCM63Z818 MCM63Z736TQ133 MCM63Z736TQ100 MCM63Z736TQ133R MCM63Z736TQ100R MCM63Z818TQ133 MCM63Z818TQ100 MCM63Z818TQ133R MCM63Z818TQ100R Motorola
Motorola => Freescale
Description : 128K x 36 and 256K x 18 Bit Pipelined ZBT™ RAM Synchronous Fast Static RAM View

The ZBT RAM is a 4M–bit Synchronous Fast Static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
    MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Two–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package

Part Name(s) : MCM63Z737 MCM63Z819 MCM63Z737TQ11 MCM63Z737TQ15 MCM63Z737TQ11R MCM63Z737TQ15R MCM63Z819TQ11 MCM63Z819TQ15 MCM63Z819TQ11R MCM63Z819TQ15R Motorola
Motorola => Freescale
Description : 128K x 36 and 256K x 18 Bit Flow–Through ZBT™ RAM Synchronous Fast Static RAM View

The ZBT RAM is a 4M–bit Synchronous Fast Static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z737 is organized as 128K words of 36 bits each and the MCM63Z819 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology.

• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z737/MCM63Z819–11 = 11 ns Access/15 ns Cycle (66 MHz)
    MCM63Z737/MCM63Z819–15 = 15 ns Access/20 ns Cycle (50 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Single–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package

Part Name(s) : HM62G18512BP-4 HM62G18512BP-5 HM62G18512 Hitachi
Hitachi -> Renesas Electronics
Description : 8M Synchronous Fast Static RAM (512k-word × 18-bit) View

Description
The HM62G18512 is a Synchronous Fast Static RAM organized as 512-kword × 18-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA.

Features
• Power supply: 3.3 V +10%, –5%
• Clock frequency: 200 MHz to 250 MHz
• Internal self-timed late write
• Byte write control (2 byte write selects, one for each 9-bit)
• Optional ×36 configuration
• HSTL compatible I/O
• ProgRAMmable impedance output drivers
• User selective input trip-point
• Differential, HSTL clock inputs
• ASynchronous G output control
• ASynchronous sleep mode
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single clock register-register mode


Part Name(s) : MCM63P736 MCM63P818 MCM63P736TQ133 MCM63P736TQ100 MCM63P736TQ66 MCM63P736TQ133R MCM63P736TQ100R MCM63P736TQ66R MCM63P736ZP133 MCM63P736ZP100 Motorola
Motorola => Freescale
Description : 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM View

The MCM63P736 and MCM63P818 are 4M bit Synchronous Fast Static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
    MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)
    MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Two–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

Part Name(s) : MCM69L817 MCM69L817ZP6 MCM69L817ZP6.5 MCM69L817ZP7 MCM69L817ZP6R MCM69L817ZP6.5R MCM69L817ZP7R Motorola
Motorola => Freescale
Description : 256K x 18 Bit Data Latch BurstRAMSynchronous Fast Static RAM View

The MCM69L817 is a 4M bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69L817 Speed Options
• 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Part Name(s) : HM64YGB36100 HM64YGB36100BP-33 Renesas
Renesas Electronics
Description : 32M Synchronous Late Write Fast Static RAM (1-Mword × 36-bit) View

Description
The HM64YGB36100 is a Synchronous Fast Static RAM organized as 1-Mword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA.

Features
• 2.5 V ± 5% operation and 1.5 V (VDDQ)
• 32-Mbit density
Synchronous register to register operation
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• ProgRAMmable impedance output drivers
• Differential HSTL clock inputs
• ASynchronous G output control
• ASynchronous sleep mode
• FC-BGA 119pin package with SRAM JEDEC standard pinout
• Limited set of boundary scan JTAG IEEE 1149.1 compatible

Part Name(s) : MCM69F735 MCM69F735ZP6 MCM69F735ZP6.5 MCM69F735ZP7 MCM69F735ZP6R MCM69F735ZP6.5R MCM69F735ZP7R Motorola
Motorola => Freescale
Description : 128K x 36 Bit Flow–Through BurstRAMSynchronous Fast Static RAM View

The MCM69F735 is a 4M bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 36 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69F735 Speed Options
• 3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

Part Name(s) : MCM69P818 MCM69P818ZP3.5 MCM69P818ZP3.8 MCM69P818ZP4 MCM69P818ZP3.5R MCM69P818ZP3.8R MCM69P818ZP4R Motorola
Motorola => Freescale
Description : 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM View

The MCM69P818 is a 4M bit Synchronous Fast Static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM69P818–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
    MCM69P818–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
    MCM69P818–4: 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• 2–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• PB1 Version 2.0 Compatible
• JEDEC Standard 119–Pin PBGA Package

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