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Part Name(s) : CY7C1362C-166BGI CY7C1362C-166BGXI CY7C1362C-166BZI Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Pipelined SRAM View

Functional Description[1]
The CY7C1360C/CY7C1362C SRAM integrates 256K x 36 and 512K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for Pipelined operation
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O operation (VDDQ)
• Fast clock-to-output times
    — 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan

Part Name(s) : CY7C1361C-133BZXI CY7C1361C-133BGXC CY7C1361C-100BGXI CY7C1361C-133BGXI CY7C1361C-100BZXC CY7C1361C-100BZXI CY7C1361C-133BZXC CY7C1361C-100BGXC CY7C1361C-100AXE Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM View

Functional Description[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• Supports 100, 133-MHz bus operations
• Supports 100-MHz bus operations (Automotive)
256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option

Part Name(s) : A67L8316E-45 A67L8316E-6 AMICC
AMIC Technology
Description : 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM View

General Description
The AMIC Direct Bus Alternation™ (DBA™ ) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8316, A67L8318, A67L7332, A67L7336 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers.

Features
● Fast access time: 4.0/4.2/4.5/5.0 ns (143,133,117,100MHz)
● Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization
● Signal +3.3V ±5% power supply
● Individual Byte Write control capability
● Clock enable (CEN) pin to enable clock and suspend operations
● Clock-controlled and registered address, data and control signals
● Registered output for Pipelined applications
● Three separate chip enables allow wide range of options for CE control, address pipelining
● Internally self-timed write cycle
● Selectable BURST mode (Linear or Interleaved)
● SLEEP mode (ZZ pin) provided
● Available in 100 pin LQFP package

Part Name(s) : A67P8336 A67P8336E-2.6 A67P8336E-2.6F A67P8336E-2.8 A67P8336E-2.8F A67P8336E-3.2 A67P8336E-3.2F A67P8336E-3.5 A67P8336E-3.5F A67P8336E-3.8 AMICC
AMIC Technology
Description : 512K X 18, 256K X 36 LVTTL, Pipelined ZeBL™ SRAM View

General Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P9318, A67P8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.



Features

■ Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)

■ Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization

■ Signal +2.5V ± 5% power supply

■ Individual Byte Write control capability

■ Clock enable ( CEN) pin to enable clock and suspend operations

■ Clock-controlled and registered address, data and control signals

■ Registered output for Pipelined applications

■ Three separate chip enables allow wide range of options for CE control, address pipelining

■ Internally self-timed write cycle

■ Selectable BURST mode (Linear or Interleaved)

■ SLEEP mode (ZZ pin) provided

■ Available in 100 pin LQFP package



 



Part Name(s) : A67L8316 A67L8318 A67L7332 A67L7336 A67L8316E A67L8318E A67L7332E A67L7336E A67L7332E-4 A67L7332E-4.2 AMIC
AMIC Technology
Description : 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM View

General Description
The AMIC Direct Bus Alternation™ (DBA™ ) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8316, A67L8318, A67L7332, A67L7336 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers.

Features
● Fast access time: 4.0/4.2/4.5/5.0 ns (143,133,117,100MHz)
● Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization
● Signal +3.3V ±5% power supply
● Individual Byte Write control capability
● Clock enable (CEN) pin to enable clock and suspend operations
● Clock-controlled and registered address, data and control signals
● Registered output for Pipelined applications
● Three separate chip enables allow wide range of options for CE control, address pipelining
● Internally self-timed write cycle
● Selectable BURST mode (Linear or Interleaved)
● SLEEP mode (ZZ pin) provided
● Available in 100 pin LQFP package

Part Name(s) : CY7C1352G-250AXC CY7C1352G-250AXI CY7C1352G-200AXC CY7C1352G-200AXI CY7C1352G-166AXC CY7C1352G-166AXI CY7C1352G CY7C1352G-133AXI CY7C1352G CY7C1352G-133AXC Cypress
Cypress Semiconductor
Description : 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture View

4-Mbit (256Kx18) Pipelined SRAM with NoBL™ Architecture

Features
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate
   the need to use OE
• Byte Write capability
256K x 18 common I/O architecture
• Single 3.3V power supply
• 2.5V / 3.3V I/O Operation
• Fast clock-to-output times
• 2.6 ns (for 250-MHz device)
• 2.8 ns (for 200-MHz device)
• 3.5 ns (for 166-MHz device)
• 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Pb-Free 100 TQFP package
• Burst Capability—linear or interleaved burst order
• ZZ” Sleep Mode Option and Stop Clock option

Part Name(s) : MCM72JG32 MCM72JG64 MCM72JG32SG66 MCM72JG64SG66 Motorola
Motorola => Freescale
Description : 256K and 512K Pipelined BurstRAM™ Sedcondary Cache Module for Pentium™ View

The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The modules are configured as 32K x 64 and 64K x 64 bits in a 160 pin card edge memory module. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the tag RAM.

• Pentium–Style Burst Counter on Chip
Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM 9 ns for Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes
• I/Os are 3.3 V Compatible on Data RAMs
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Series 20 Ω Resistors for Noise Immunity

Part Name(s) : CY7C1361B CY7C1361B-117AC CY7C1361B-117AI CY7C1361B-117AJC CY7C1361B-117AJI CY7C1361B-117BGC CY7C1361B-117BGI CY7C1361B-117BZC CY7C1361B-117BZI CY7C1361B-133AC Cypress
Cypress Semiconductor
Description : 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM View

Functional Description[1]
The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• Supports 133-MHz bus operations
256K X 36/512K X 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133-MHz version)
    — 7.5 ns (117-MHz version)
    — 8.5 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-ball fBGA packages
    — Both 2 and 3 Chip Enable Options for TQFP
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option

Part Name(s) : CY7C1354A CY7C1354A-133 CY7C1354A-133BGC CY7C1354A-133BGI CY7C1354A-166 CY7C1354A-166AC CY7C1354A-166BGC CY7C1354A-166BGI CY7C1354A-200 CY7C1354A-200AC Cypress
Cypress Semiconductor
Description : 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture View

Functional Description

The CY7C1354A and CY7C1356A SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa. These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency™ (ZBL™)/No Bus Latency™ (NoBL™). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. These employ high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.



Features

• Zero Bus Latency™, no dead cycles between Write and Read cycles

• Fast clock speed: 200, 166, 133, 100 MHz

• Fast access time: 3.2, 3.6, 4.2, 5.0 ns

• Internally synchronized registered outputs eliminate the need to control OE

• Single 3.3V –5% and +5% power supply VCC

• Separate VCCQ for 3.3V or 2.5V I/O

• Single WEN (Read/Write) control pin

• Positive clock-edge triggered, address, data, and control signal registers for fully Pipelined applications

• Interleaved or linear four-word burst capability

• Individual byte Write (BWa–BWd) control (may be tied LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Automatic power-down feature available using ZZ mode or CE select

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array), and 100-pin TQFP packages



 


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