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GSI
Giga Semiconductor
Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description

The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.



Features

• User-configurable Pipeline and Flow Through mode

NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization

• Fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard packages

• Pb-Free 100-lead TQFP package available



 


Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description

The GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.



Features

• User-configurable Pipeline and Flow Through mode

NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization

• Fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard packages



 


Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS882Z18/36B is a 9Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA packages

Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS882Z18/36B is a 9Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA packages

Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package

Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

[GSI]

Functional Description
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package

Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS881Z18/36AT is a 9Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
• User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP package

Description : 288Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS82564Z18/36-xxxV is a 288Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
   
Features
NBT (No Bus Turn Around) functionality allows zero wait
    Read-Write-Read bus utilization; fully pin-compatible with
    both Pipelined and Flow Through NtRAM™, NoBL™ and
    ZBT™ SRAMs
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb
    devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• RoHS-compliant 119- and 165-bump BGA packages
   

Description : 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS881Z18B(T/D)/GS881Z32B(D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
• User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin-compatible with both Pipelined and Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages

Description : 288Mb Pipelined and Flow Through Synchronous NBT SRAM

Functional Description
The GS82564Z18/36 is a 288Mbit Synchronous Static SRAM.
GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other Pipelined read/double late write or Flow Through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
   
Features
NBT (No Bus Turn Around) functionality allows zero wait
    Read-Write-Read bus utilization; fully pin-compatible with
    both Pipelined and Flow Through NtRAM™, NoBL™ and
    ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb
    devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• RoHS-compliant 119- and 165-bump BGA packages
   

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