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Description : 4M x 36-Bit EDO - DRAM Module

The HYM 364025S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by 36-Bit in a 72-pin single-in-line package comprising eight HYB 5117405BJ 4M × 4 EDO-DRAMs and four HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages mounted together with ceramic decoupling capacitors on a PC board.

• SIMM modules with 4 194 304 words by 36-Bit organization for PC main memory applications
• Fast access and cycle time
    50 ns access time
    84 ns cycle time (-50 version)
    60 ns access time
    104 ns cycle time (-60 version)
• Hyper Page Mode (EDO) capability
    20 ns cycle time (-50 version)
    25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
    max. 6820 mW active (-50 version)
    max. 6160 mW active (-60 version)
    CMOS – 66 mW standby
    TTL –132 mW standby
• CAS-before-RAS refresh
    RAS-only-refresh
    Hidden-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-12) with 22.9 mm (900 mil) height
• Utilizes eight 4Mx4-EDO-DRAMs and four 4Mx1-EDO-DRAMs in SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write parity applications
• Tin-Lead contact pads (S-version)
• Gold contact pads (GS - version)

Description : 8M x 36-Bit EDO - DRAM Module

The HYM 368025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 36- Bit in two banks in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M × 4 EDO-DRAMs and eight HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages mounted together with decoupling capacitors on a PC board.

• SIMM modules with 8 388 608 words by 36-bit organization in two banks for PC main memory applications
• Fast access and cycle time
    50 ns access time
    84 ns cycle time (-50 version)
    60 ns access time
    104 ns cycle time (-60 version)
• Hyper Page Mode (EDO) capability
    20 ns cycle time (-50 version)
    25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
    max. 6820 mW active (-50 version)
    max. 6160 mW active (-60 version)
    CMOS – 132 mW standby
    TTL –264 mW standby
• CAS-before-RAS refresh
    RAS-only-refresh
    Hidden-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-14) with 31.75 mm height
• Utilizes sixteen 4Mx4-EDO-DRAMs and eight 4M x 1 EDO-DRAMs in 300 mil wide SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write parity applications
• Tin-Lead contact pads (S- version)
• Gold contact pads (GS - version)

Description : 4M x 36-Bit EDO - DRAM Module

The HYM 364025S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by 36-Bit in a 72-pin single-in-line package comprising eight HYB 5117405BJ 4M × 4 EDO-DRAMs and four HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages mounted together with ceramic decoupling capacitors on a PC board.

• SIMM modules with 4 194 304 words by 36-Bit organization for PC main memory applications
• Fast access and cycle time
    50 ns access time
    84 ns cycle time (-50 version)
    60 ns access time
    104 ns cycle time (-60 version)
• Hyper Page Mode (EDO) capability
    20 ns cycle time (-50 version)
    25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
    max. 6820 mW active (-50 version)
    max. 6160 mW active (-60 version)
    CMOS – 66 mW standby
    TTL –132 mW standby
• CAS-before-RAS refresh
    RAS-only-refresh
    Hidden-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-12) with 22.9 mm (900 mil) height
• Utilizes eight 4Mx4-EDO-DRAMs and four 4Mx1-EDO-DRAMs in SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write parity applications
• Tin-Lead contact pads (S-version)
• Gold contact pads (GS - version)

Infineon
Infineon Technologies
Description : 8M x 36-Bit EDO - DRAM Module

The HYM 368025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 36- Bit in two banks in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M × 4 EDO-DRAMs and eight HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages mounted together with decoupling capacitors on a PC board.

• SIMM modules with 8 388 608 words by 36-bit organization in two banks for PC main memory applications
• Fast access and cycle time
    50 ns access time
    84 ns cycle time (-50 version)
    60 ns access time
    104 ns cycle time (-60 version)
• Hyper Page Mode (EDO) capability
    20 ns cycle time (-50 version)
    25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
    max. 6820 mW active (-50 version)
    max. 6160 mW active (-60 version)
    CMOS – 132 mW standby
    TTL –264 mW standby
• CAS-before-RAS refresh
    RAS-only-refresh
    Hidden-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-14) with 31.75 mm height
• Utilizes sixteen 4Mx4-EDO-DRAMs and eight 4M x 1 EDO-DRAMs in 300 mil wide SOJ packages
• 2048 refresh cycles / 32 ms
• Optimized for use in byte-write parity applications
• Tin-Lead contact pads (S- version)
• Gold contact pads (GS - version)

Description : ASCEND Semiconductor 4Mx4 EDO

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Description : ASCEND Semiconductor 4Mx4 EDO

Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features
• Single 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)

Description : 3.3V 1M × 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module

3.3V 1M × 64-Bit EDO-DRAM Module
3.3V 1M x 72-Bit EDO-DRAM Module
168pin unbuffered DIMM Module with serial presence detect

The HYM64(72)V1005GU-50/-60 are industry standard 168-pin 8-byte Dual In-Line Memory Module (DIMMs) which are organized as 1M x 64 and 1M x 72 high speed memory arrays designed with EDO DRAMs for non-parity and ECC applications. The DIMMs use four 1M x 16 EDO DRAMs for the 1M x 64 organisation and additional two 1M x 4 DRAMs for the 1M x 72 organisation. Decoupling capacitors are mounted on the PC board.

• 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications
• 1 bank 1M x 64, 1M x 72 organisation
• Optimized for byte-write non-parity or ECC applications
• Extended Data Out (EDO)
• Performance:
• Single +3.3 V ± 0.3 V Power Supply
• CAS-before-RAS refresh, RAS-only-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks are fully LV-TTL compatible
• Serial presence detects (optional)
• Utilizes four 1M × 16 -DRAMs in TSOPII-50/44 and two 1M x 4 - DRAMs in SOJ 26/20 packages
• 1024 refresh cycles / 16 ms with 10 / 10 addressing (Row / Column)
• Gold contact pad
• Card Size: 133,35mm x 25,40 mm x 5,30 mm
• This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family

Description : 3.3V 2M × 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module

3.3V 2M × 64-Bit EDO-DRAM Module
3.3V 2M x 72-Bit EDO-DRAM Module
168pin unbuffered DIMM Module with serial presence detect

The HYM64(72)V2005GU-50/-60 are industry standard 168-pin 8-byte Dual In-Line Memory Modules (DIMMs) which are organized as 2M x 64 and 2M x 72 high speed memory arrays designed with EDO DRAMs for non-parity and ECC applications. The DIMMs use eight 2M x 8 EDO DRAMs for the 2M x 64 organisation and nine 2M x 8 DRAMs for the 2M x 72 organisation, both in SOJ packages. Decoupling capacitors are mounted on the PC board.

• 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications
• 1 bank 2M x 64, 2M x 72 organisation
• Optimized for byte-write non-parity or ECC applications
• Extended Data Out (EDO)
• Performance:
• Single +3.3 V ± 0.3 V Power Supply
• CAS-before-RAS refresh, RAS-only-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks are fully LV-TTL compatible
• Serial presence detects (optional)
• Utilizes 2M × 8 -DRAMs in SOJ packages
• 2048 refresh cycles / 32 ms with 11 / 10 addressing (Row / Column)
• Gold contact pad
• Card Size: 133,35mm x 25,40 mm x 5,30 mm
• This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family

Description : 3.3V 4M × 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module

3.3V 4M × 64-Bit EDO-DRAM Module
3.3V 4M x 72-Bit EDO-DRAM Module
168pin unbuffered DIMM Module with serial presence detect

The HYM64(72)V4005/45GU-50/-60 are industry standard 168-pin 8-byte Dual In-Line Memory Modules (DIMMs) which are organized as 4M x 64 and 4M x 72 high speed memory arrays designed with EDO DRAMs for non-parity and ECC applications. 2k refresh with 11 / 11 addressing and 4k refresh modules with 12 / 10 addressing are available. The DIMMs use sixteen 4M x 4 EDO DRAMs for the 4M x 64 organisation and eighteen 4M x 4 DRAMs for the 4M x 72 organisation, both in TSOPII packages. Decoupling capacitors are mounted on the PC board.

• 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications
• 1 bank 4M x 64, 4M x 72 in 2k and 4k refresh organisations
• Optimized for byte-write non-parity or ECC applications
• Extended Data Out (EDO)
• Performance:
• Single +3.3 V ± 0.3 V Power Supply
• CAS-before-RAS refresh, RAS-only-refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs and clocks are fully LV-TTL compatible
• Serial presence detects (optional)
• Utilizes 4M x 4 -DRAMs in TSOPII packages
• 2048 refresh cycles / 32 ms with 11 / 11 addressing ( Row / Column) for HYM64/72V4005GU
• 4096 refresh cycles / 64 ms with 12 / 10 addressing ( Row / Column) for HYM64/72V4045GU
• Gold contact pads
• Card Size: 133,35mm x 25,40 mm x 4,00 mm
• This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family

Description : 3.3V 256 K x 16-Bit EDO-DRAM 3.3V 256 K x 16-Bit EDO-DRAM (Low power version with Self Refresh)

3.3V 256 K x 16-Bit EDO-DRAM
3.3V 256 K x 16-Bit EDO-DRAM
(Low power version with Self Refresh)

The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (L-Version), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic device families.

Preliminary Information
• 262 144 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast access and cycle time
• RAS access time:
   50 ns (-50 version)
   55 ns (-55 version)
   60 ns (-60 version)
• CAS access time:
   13ns (-50 & -55 version)
   15 ns (-60 version)
• Cycle time:
   89 ns (-50 version)
   94 ns (-55 version)
   104 ns (-60 version)
• Hype page mode (EDO) cycle time
   20 ns (-50 & -55 version)
   25 ns (-60 version)
• High data rate
   50 MHz (-50 & -55 version)
   40 MHz (-60 version)
• Single + 3.3 V (±0.3 V) supply with a builtin VBB generator
• Low Power dissipation
   max. 450 mW active (-50 version)
   max. 432 mW active (-55 version)
   max. 378 mW active (-60 version)
• Standby power dissipation
   7.2 mW standby (TTL)
   3.6 mW max. standby (CMOS)
   0.72 mW max. standby (CMOS) for
   Low Power Version
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CASbefore-RAS refresh, RAS-only refresh, hidden-refresh and hyper page (EDO) mode capability
• 2 CAS / 1 WE control
• Self Refresh (L-Version)
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms
• 512 refresh cycles / 128 ms
   Low Power Version only
• Plastic Packages:
   P-SOJ-40-1 400mil width

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