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The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 Interface provides a single-access ATM service termination for User-to-Network (UNI) and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751, G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise Equipment (CPE) and switching system Interface functions are provided.

Distinguishing Features
• Integrates 7 line framers with ATM
   layer processing according to ATM
   Forum UNI and NNI Specifications
• UTOPIA Level 1 Interface
• Internal framers for DS3, E3 (G.751,
   G.832), E4 (G.832), STS-1, STS-3c,
   STM-1
• PLCP and G.804 HEC cell alignment
   for all data rates from 1.544 Mbps to
   155 Mbps
• Direct Interface to TAXITM or external
   T1/E1 framers
• ATM and SMDS cell modes
• 4 FIFO ports with header screening,
   formatting, and transmit priority
   controls
• Idle cells generated and screened
• Statistics counts latched on
   one-second intervals
• Error detection and insertion
• Option insertion or generation of all
   line and cell overhead
• Serial or parallel line Interface
• Available evaluation module
   reference design and software
• Supports Automatic Protection
   Switching (APS)

Applications
• WAN equipment
• ATM switches
• Test equipment
• ATM routers and hub

Low-Profile ATM Fuses
32Vdc, 5 to 30A Fast-Acting Automotive Blade Fuse

Features
• Similar performance characteristics as the standard MINI fuse.
• Lower overall height allows for more space and weight savings.
• Designed to mate with tuning-fork terminals for additional weight and material savings in fuse panel designs (eliminates the need for female box terminals).

The TE3-FALC® is a complete solution for a T3/E3 broadband Interface. It includes DS3/E3 framing, analog line Interface, two jitter attenuators and the mapping of ATM or PPP/HDLC. The TE3-FALC® also integrates a microcontroller which is running the device driver and gathering statistics as managed MIB objects.
On the line side the TE3-FALC® Interfaces to a 75 Ω co-axial cable via transformers. Highly accurate analog pulse shaping removes the need to measure cable length and set the Line Build Out.  On the system side, industry standard UTOPIA and POS-PHY Interface as well as a serial clock/data port are provided. This allows the TE3-FALC® to be connected to a wide array of Layer 2/3 & 4 network processors.

Key Features
■ Integrated T3/E3 analog
■ Single pulse template for all line lengths, no LBO requirement
■ Jitter attenuation in both Tx and Rx
■ Full featured DS3/E3 framer
■ ATM and PPP/HDLC mapping
■ UTOPIA or POS-PHY Interface
■ Integrated µC running S/W driver
■ Control via 8/16 Bit Motorola/Intel µP i/f or inband ATM/PPP messages
■ High level message based API

Applications
■ Wireless base stations
■ LAN/WAN router
■ DSLAMs
■ Remote access/concentrator
■ Multimedia gateways

Dual Universal Asynchronous Receiver/Transmitter with FIFOs plus High Performance Parallel Interface

GENERAL DESCRIPTION
The XRT72L71 DS3 ATM User Network Interface (UNI)/Clear-Channel Framer is designed to function as either a DS3 ATM UNI or Clear channel framer. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) Interface for both the public and private networks at DS3 rates. For Clear-Channel framer applications, this device supports the transmission and reception of “user data” via the DS3 payload bits.

FEATURES
• Compliant with UTOPIA Level 1 and 2 with 8 or 16 Bit Interface Specification and supports UTOPIA Bus speeds of up to 50 MHz
• Contains on-chip 16 cell FIFO in both the Transmit (TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit OAM Cell buffer and a 108 byte Receive OAM cell buffer, for transmission, reception and processing of OAM cells.
• Supports PLCP or ATM Direct Mapping modes
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3 Clear Channel Framing Applications
• Includes PRBS Generator and Receiver
• Supports Local, Remote-Line, Cell, and PLCP Loop-backs
• Interfaces to 8 or 16 Bit wide Motorola and Intel µPs
• Low power 3.3V, 5V input tolerant, CMOS
• 160 pin PQFP Package
• 3 and 4 Channel Version also Available

APPLICATIONS
• Private User Network Interfaces
• ATM Switches
• ATM Concentrators
• DSLAM Equipment
• DS3 Frame Relay Equipment

GENERAL DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul applications. The backplane is user-configurable for a TDM or UTOPIA II bus Interface. The DS2156 is composed of a line Interface unit (LIU), framer, HDLC controllers, and a UTOPIA/TDM backplane Interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155.

FEATURES
■ Complete T1/DS1/ISDN-PRI/J1 Transceiver Functionality
■ Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality
■ User-Selectable TDM or UTOPIA II Bus Interface
■ Long-Haul and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping
■ CMI Coder/Decoder for Optical I/F
■ Crystal-Less Jitter Attenuator
■ Fully Independent Transmit and Receive Functionality
■ Dual HDLC Controllers
■ Programmable BERT Generator and Detector
■ Internal Software-Selectable Receive and Transmit-Side Termination Resistors for 75Ω/100Ω/120Ω T1 and E1 Interfaces
■ Dual Two-Frame Elastic-Store Slip Buffers that Connect to Asynchronous Backplanes Up to 16.384MHz
■ 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Network Clock

APPLICATIONS
    Inverse Mux ATM (IMA)
    T1/E1/J1 Line Cards
    Switches and Routers
    Add-Drop Multiplexers

Description
The HFBR-1116/-2116 series of data links are high-performance, cost-efficient, transmitter and receiver modules for serial optical data communication applications specified at 155 MBd for ATM UNI applications.

Features
• Full Compliance with the Optical Performance Requirements of the ATM Forum UNI SONET OC-3 Multimode Physical Layer Specification
• Other Versions Available for: - FDDI - Fibre Channel
• Compact 16-pin DIP Package with Plastic ST* Connector
• Wave Solder and Aqueous Wash Process Compatible Package
• Manufactured in an ISO 9001 Certified Facility

Applications
• ATM Switches, Hubs, and Network Interface Cards
• Multimode Fiber ATM Wiring Closet-to-Desktop Links
• Point-to-Point Data Communications
• Replaces DLT/R1040-ST1 Model Transmitters and Receivers

Description
The HFBR-1116TZ/-2116TZ series of data links are high performance, cost-efcient, transmitter and receiver modules for serial optical data communication applications specifed at 155 Mbps for ATM UNI applications.

Features
•  Full compliance with the optical performance requirements of the ATM Forum UNI SONET OC-3 multimode physical layer specifcation
•  Other versions available for: – FDDI – Fibre Channel
•  Compact 16-pin DIP package with plastic ST* connector
•  Wave solder and aqueous wash process compatible package
•  Manufactured in an ISO 9001 certifed facility

Applications
•  ATM switches, hubs, and network Interface cards
•  Multimode fber ATM wiring closet-to-desktop links
•  Point-to-point data communications
•  Replaces DLT/R1040-ST1 model transmitters and receivers

DESCRIPTION

The Philips Semiconductors SCC68692 Dual Universal Asynchronous Receiver/Transmitter (DUART) is compatible with SCN68681. It is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It is compatible with other S68000 family devices and can also Interface easily with other microprocessors. The DUART can be used in a polled or interrupt driven systems.