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Part Name(s) : TC4017 TC4017BF TC4017BP
Description : TC4017BP/TC4017BF Decade Counter/Divider
Toshiba
Toshiba

TC4017BP/BF is decimal Johnson counter consisting of 5 stage D-type flip-flop equipped with the decoder to convert the output to decimal. Depending on the number of count pulses fed to CLOCK or CLOCK INHIBIT one output among 10 output lines “Q0” through “Q9” becomes “H” level. The counter advances its state at rising edge of CLOCK (CLOCK INHIBIT = “L”) or falling edge of CLOCK INHIBIT (CLOCK = “H”). RESET input to “H” level resets the counter to Q0 = “H” and Q1 through Q9 = “L” regardless of CLOCK and CLOCK INHIBIT

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Part Name(s) : IDT2305 IDT2305-1DC IDT2305-1DCG IDT2305-1DCGI IDT2305-1DCI IDT2305-1HDC IDT2305-1HDCI IDT2305-1PGG IDT2305-1PGGI
Description : 3.3V ZERO DELAY CLOCK BUFFER
IDT
Integrated Device Technology

The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

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Part Name(s) : XRK79892 XRK79892IQ
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
Exar
Exar Corporation

GENERAL DESCRIPTION
The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packagin
• Pin compatible with MPC9892i

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Part Name(s) : XRK7988
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
Exar
Exar Corporation

GENERAL DESCRIPTION
The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 8x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packaging
• 19.44 to 155.52 MHz

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Part Name(s) : NJU6359 NJU6359C NJU6359V
Description : SERIAL I/O REAL TIME CLOCK WITH WAKE-UP OUTPUT for EXTERNAL CLOCK
JRC
Japan Radio Corporation
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Part Name(s) : LMK04906 LMK04906BISQ LMK04906BISQ/NOPB LMK04906BISQE LMK04906BISQE/NOPB LMK04906BISQX LMK04906BISQX/NOPB
Description : Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs / 64-Pin WQFN (9.0 x 9.0 x 0.8 mm)
TI
Texas Instruments

The LMK04906 is the industry's highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.

The LMK04906 accepts 3 clock input ranging from 1 kHz to 750 MHz and generates 6 unique clock output frequencies ranging from 2.26 MHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7th unique clock frequency.

The device provides virtually all frequency translation combination required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.

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Part Name(s) : SN54LS73 SN54LS73AJ SN54LS73J SN74LS73 SN74LS73A SN74LS73AD SN74LS73AN SN74LS73D SN74LS73N
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola
Motorola => Freescale

  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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Part Name(s) : SN54LS113A SN54LS113AJ SN54LS113J SN74LS113AD SN74LS113AN SN74LS113D SN74LS113N
Description : Dual JK negative edge-triggered flip-flop
Motorola
Motorola => Freescale

The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithicdual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputsmay be allowed to change when the clock pulse is HIGH and the bistablewill perform according to the truth table as longas minimum setup timesare observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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Part Name(s) : ICS541 ICS541M ICS541MT
Description : PLL Clock Divider
ICST
Integrated Circuit Systems

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. So, for instance, if an 80 MHz input clock is used, the ICS541 can produce low skew 80 MHz and 40 MHz clocks, or 40 MHz and 20 MHz clocks, or 20 MHz and 10MHz clocks. The chip has an all-chip power down mode that stops the outputs low, and an OE pin that tristates the outputs.
The ICS541 is a member of the ICS ClockBlocks™ family of clock building blocks. See the ICS542 and ICS543 for other clock dividers, and the ICS300, 501, 502, and 503 for clock multipliers. Description

Features
• Packaged in 8 pin SOIC
• Low cost clock divider
• Low skew (500ps) outputs. One is ÷ 2 of other.
• Easy to use with other generators and buffers
• Input clock frequency up to 135 MHz at 3.3 V
• Input clock frequency up to 156 MHz at 5.0 V
• Tolerant of poor input clock duty cycle, jitter.
• Output clock duty cycle of 45/55
• Power Down turns off chip
• Output Enable
• Full CMOS clock swings with 25mA drive capability at TTL levels
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V

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Part Name(s) : HD74LS165A HD74LS165AFP HD74LS165AFPEL HD74LS165AP
Description : Parallel-Load 8-bit Shift Register
Renesas
Renesas Electronics

The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift / load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift / load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the clock, clock inhibit, or serial inputs

 

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