P/N + Description + Content Search


1 2 3 4 5 6 7 8 9 10 Next

Part Name(s) : TC4017 TC4017BF TC4017BP
Description : TC4017BP/TC4017BF Decade Counter/Divider
Toshiba
Toshiba

TC4017BP/BF is decimal Johnson counter consisting of 5 stage D-type flip-flop equipped with the decoder to convert the output to decimal. Depending on the number of count pulses fed to CLOCK or CLOCK INHIBIT one output among 10 output lines “Q0” through “Q9” becomes “H” level. The counter advances its state at rising edge of CLOCK (CLOCK INHIBIT = “L”) or falling edge of CLOCK INHIBIT (CLOCK = “H”). RESET input to “H” level resets the counter to Q0 = “H” and Q1 through Q9 = “L” regardless of CLOCK and CLOCK INHIBIT

View
Part Name(s) : XRK7988
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
Exar
Exar Corporation

GENERAL DESCRIPTION
The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 8x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packaging
• 19.44 to 155.52 MHz

View
Part Name(s) : XRK79892 XRK79892IQ
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
Exar
Exar Corporation

GENERAL DESCRIPTION
The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packagin
• Pin compatible with MPC9892i

View
Part Name(s) : MPC9449 MPC9449 MPC9449_16
Description : 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer
IDT
Integrated Device Technology

The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications.

Features
• 15 LVCMOS compatible clock outputs
• Two selectable LVCMOS and one differential LVPECL compatible clock inputs
• Selectable output frequency divider (divide-by-one and divide-by-two)
• Maximum clock frequency of 200 MHz
• Maximum clock skew of 200 ps
• High-impedance output control
• 3.3 V or 2.5 V power supply
• Drives up to 30 series terminated clock lines
• Ambient temperature range –40C to +85C
• 52-lead LQFP packaging, Pb-free
• Supports clock distribution in networking, telecommunication
   and computing applications
• Pin and function compatible to MPC949

View
Part Name(s) : CDC1104 CDC1104RVKR
Description : 1 to 4 Configurable Clock Buffer for 3D Displays
TI
Texas Instruments

DESCRIPTION
The CDC1104 is a 1 to 4 configurable clock buffer. The device accepts an input reference clock and creates 4 buffered output clocks with an output frequency equal to one half the input clock frequency. Four control inputs, S1, S2, S3, S4 configurable phases of the clock outputs.

FEATURES
• Input Reference Clock 120Hz–240Hz
• Output Clock (Fin/2) 60Hz–120Hz
• Output Buffer Drive Strength: 8mA
• 4 Clock Outputs
• 4 Control Pins Select Phases of Clock Outputs
• Supply Voltage: 3.8V–5.5V
• Operating Temperature Range: –40°C to 85°C
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-B)
   – 500-V Charged-Device Model (C101)
• Package Offerings
   – 12-pin QFN (3mm x 3mm)

View
Part Name(s) : IDT2305 IDT2305-1DC IDT2305-1DCG IDT2305-1DCGI IDT2305-1DCI IDT2305-1HDC IDT2305-1HDCI IDT2305-1PGG IDT2305-1PGGI
Description : 3.3V ZERO DELAY CLOCK BUFFER
IDT
Integrated Device Technology

The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

View
Part Name(s) : MPC9449
Description : 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer
Motorola
Motorola => Freescale

The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications.

Features
• 15 LVCMOS compatible clock outputs
• Two selectable LVCMOS and one differential LVPECL compatible clock inputs
• Selectable output frequency divider (divide-by-one and divide-by-two)
• Maximum clock frequency of 200 MHz
• Maximum clock skew of 200 ps
• High-impedance output control
• 3.3V or 2.5V power supply
• Drives up to 30 series terminated clock lines
• Ambient temperature range –40°C to +85°C
• 52 lead LQFP packaging
• Supports clock distribution in networking, telecommunication and
   computing applications
• Pin and function compatible to MPC949

View
Part Name(s) : NJU6359 NJU6359C NJU6359V
Description : SERIAL I/O REAL TIME CLOCK WITH WAKE-UP OUTPUT for EXTERNAL CLOCK
JRC
Japan Radio Corporation
View
Part Name(s) : ICS541 ICS541M ICS541MT
Description : PLL Clock Divider
ICST
Integrated Circuit Systems

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. So, for instance, if an 80 MHz input clock is used, the ICS541 can produce low skew 80 MHz and 40 MHz clocks, or 40 MHz and 20 MHz clocks, or 20 MHz and 10MHz clocks. The chip has an all-chip power down mode that stops the outputs low, and an OE pin that tristates the outputs.
The ICS541 is a member of the ICS ClockBlocks™ family of clock building blocks. See the ICS542 and ICS543 for other clock dividers, and the ICS300, 501, 502, and 503 for clock multipliers. Description

Features
• Packaged in 8 pin SOIC
• Low cost clock divider
• Low skew (500ps) outputs. One is ÷ 2 of other.
• Easy to use with other generators and buffers
• Input clock frequency up to 135 MHz at 3.3 V
• Input clock frequency up to 156 MHz at 5.0 V
• Tolerant of poor input clock duty cycle, jitter.
• Output clock duty cycle of 45/55
• Power Down turns off chip
• Output Enable
• Full CMOS clock swings with 25mA drive capability at TTL levels
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V

View
Part Name(s) : HD74LS165A HD74LS165AFP HD74LS165AFPEL HD74LS165AP
Description : Parallel-Load 8-bit Shift Register
Renesas
Renesas Electronics

The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift / load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift / load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the clock, clock inhibit, or serial inputs

 

View

1

2345678910 Next



한국어     日本語     русский     简体中文     español
@ 2015 - 2018  [ Home  ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]