P/N + Description + Content Search


1 2 3 4 5 6 7 8 9 10 Next

Part Name(s) : HD74LS293 HD74LS293P
Description : 4-bit Binary Counter
Renesas
Renesas Electronics

4-bit Binary Counter

This counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and divide by-eight counter. This counter has a gated zero reset. To use the maximum count length of this counter, the B input is connected to the QAoutput. The input count pulses are applied to input A and the outputs are as described in the appropriate function table.

 

View
Part Name(s) : HD74LS93 HD74LS93FPEL HD74LS93P
Description : 4-bit Binary Counter
Renesas
Renesas Electronics

The HD74LS93 contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and three-state binary counter for divide-by-eight. To use this maximum count length of this counter, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are described in the appropriate function table.

View
Part Name(s) : CD40192 CD40192B CD40192BMS CD40193 CD40193B CD40193BMS
Description : CMOS Presettable Up/Down Counters (Dual Clock With Reset)
Intersil
Intersil

Description
CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.

 

View
Part Name(s) : 7490 DM7490A DM7490AN
Description : Decade and Binary Counters
Fairchild
Fairchild Semiconductor

General Description
The DM7490A monolithic counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five.
The counter has a gated zero reset and also has gated setto-nine inputs for use in BCD nine’s complement applications.

Features
■ Typical power dissipation
   —90A 145 mW
■ Count frequency 42 MHz

View
Part Name(s) : HEC4020BDB HEF4020B HEF4020BDB HEF4020BDF HEF4020BF HEF4020BN HEF4020BPB HEF4020BPN HEF4020BTD HEF4020BU HEF4020BP HEF4020BD HEF4020BT
Description : 14-stage binary counter
Philips
Philips Electronics

DESCRIPTION
The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0, O3 to O13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V).

View
Part Name(s) : HEF4040 HEF4040B HEF4040BD HEF4040BF HEF4040BN HEF4040BP HEF4040BPB HEF4040BT HEF4040BU
Description : 12-stage binary counter
Philips
Philips Electronics

DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

View
Part Name(s) : MMC4017 MMC4022
Description : COUNTER/ DIVIDERS : 4017 DECADE COUNTER WITH 10 DECODED OUTPUTS
Micro-Electronics
Micro Electronics
View
Part Name(s) : HEF4520B HEF4520BD HEF4520BF HEF4520BN HEF4520BP HEF4520BT
Description : MSI Dual binary counter
Philips
Philips Electronics

DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH transition of the CP0input if CP1is HIGH or the HIGH to LOW transition of the CP1 input if CP0is low. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0to O3= LOW) independent of CP0,CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

 

View
Part Name(s) : MC10136 MC10136FN MC10136L MC10136P MC10136FNR2
Description : Universal Hexadecimal Counter
ON-Semiconductor
ON Semiconductor

The MC10136 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this device allows the designer to use one basic counter for most applications, and the synchronous count feature makes the MC10136 suitable for either computers or instrumentation.
Three control lines (S1, S2, and Carry In) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out goes low on the terminal count, or when the counter is being preset.
This device is not designed for use with gated clocks. Control is via S1 and S2.

• PD = 625 mW typ/pkg (No Load)
• fcount = 150 MHz typ
• tpd = 3.3 ns typ (C-Q)
• 7.0 ns typ (C-Cout)
• 5.0 ns typ (Cin-Cout)

View
Part Name(s) : 4017B HEF4017B HEF4017BD HEF4017BF HEF4017BN HEF4017BP HEF4017BT HEF4017BPN HEF4017BDF HEF4017BTD
Description : 5-stage Johnson counter
Philips
Philips Electronics

DESCRIPTION
The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Oo to O9), an active LOW output from the most significant flip-flop (O5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).
The counter is advanced by either a LOW to HIGH transition at CP0 while CP1 is LOW or a HIGH to LOW transition at CP1 while CP0 is HIGH (see also function table).
When cascading counters, the O5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero (Oo = O5-9 = HIGH; O1 to O9 = LOW) independent of the clock inputs (CP0, CP1).
Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

View

1

2345678910 Next



한국어     日本語     русский     简体中文     español
@ 2015 - 2018  [ Home  ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]