The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available.
The optimized architecture of the TVP5150A decoder allows for ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5150A decoder can be programmed using an I2C serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O.
The MAS 35x9F is a single-chip, low-power MPEG layer 2/3 and MPEG2-AAC audio stereo decoder. It also contains the G.729 Annex A speech compression and decompression technology for use in memory based or broadcast applications. Additional functional ity is achievable via download software (e.g., CELP voice decoder, Micronas SC4 (ADPCM) encoder/decoder).
TC4028B is a BCD-to-DECIMAL decoder which converts BCD signal into DECIMAL signal. Of ten outputs from Q0 to Q9, one output corresponding to input BCD code goes to the “H” level and all the others remain at the “L” level. When D is used as inhibit input by use of three input lines from A to C, this decoder can be served as a BINARY-to-OCTAL decoder.
The MC54/74F138 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or to a 1-of-32 decoder using four F138s and one inverter.
The various versions of the TDA955X/6X/8X H/N1 series combine the functions of a video processor together with a µ-Controller and US Closed Caption decoder. Most versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1or 10 page text. The ICs are intended to be used in economy television receivers with 90° and 110° picture tubes. The ICs have supply voltages of 8 V and 3.3 V and they
are mounted in a QFP 80 envelope.
The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using four F138 devices and one inverter.
Multiple input enable for easy expansion
Active LOW mutually exclusive outputs