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Part name(s)' : SN54LS74AJ SN74LS74A SN74LS74AD SN74LS74AN SN54LS74A
Description : Dual D-Type Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY
Motorola
Motorola => Freescale

Dual D-Type Positive Edge-Triggered Flip-Flop

The SN54/74LS74A Dual Edge-Triggered Flip-Flop utilizes Schottky TTL circuitry to produce high speed D-Type Flip-Flops. Each Flip-Flop has indiviDual clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the Positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the Positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

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Part name(s)' : 74F50728 I74F50728D I74F50728N N74F50728D N74F50728N
Description : Synchronizing cascaded Dual Positive Edge-Triggered D-Type Flip-Flop
Philips
Philips Electronics

DESCRIPTION

The 74F50728 is a cascaded Dual Positive edge–triggered D–type featuring indiviDual data, clock, set and reset inputs; also true and complementary outputs.



FEATURES

• Metastable immune characteristics

• Output skew less than 1.5ns

• See 74F5074 for synchronizing Dual D-Type Flip-Flop

• See 74F50109 for synchronizing Dual J–K Positive Edge-Triggered Flip-Flop

• See 74F50729 for synchronizing Dual Dual D-Type Flip-Flop with Edge-Triggered set and reset

• Industrial temperature range available (–40°C to +85°C)



 


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Part name(s)' : MC54F74 MC54F74J MC74F74 MC74F74D MC74F74J MC74F74N
Description : Dual D-Type Positive Edge-Triggered Flip-Flop
Motorola
Motorola => Freescale

Dual D-Type Positive Edge-Triggered Flip-Flop FAST SCHOTTKY TTL


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Part name(s)' : SN74LS74A SN74LS74AN SN74LS74AD
Description : Dual D−Type Positive Edge−Triggered Flip−Flop
ONSEMI
ON Semiconductor

The SN74LS74A Dual Edge-Triggered Flip-Flop utilizes Schottky TTL circuitry to produce high speed D-Type Flip-Flops. Each Flip-Flop has indiviDual clear and set inputs, and also complementary Q and Q outputs.

Information at input D is transferred to the Q output on the Positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the Positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
   

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Part name(s)' : SN54LS109AJ SN74LS109A SN74LS109AD SN74LS109AN
Description : Dual JK Positive Edge-Triggered Flip-Flop
Motorola
Motorola => Freescale

Dual JK Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY



The SN54/74LS109A consists of two high speed completely independent transition clocked JK Flip-Flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D Flip-Flop by simply connecting the J and Kpins together.


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Part name(s)' : 74F50109 N74F50109D N74F50109N
Description : Synchronizing Dual J-K Positive Edge-Triggered Flip-Flop with metastable immune characteristics
Philips
Philips Electronics

FEATURE

• Metastable immune characteristics

• Output skew guaranteed less than 1.5ns

• High source current (IOH = 15mA) ideal for clock driver applications

• Pinout compatible with 74F109

• See 74F5074 for synchronizing Dual D-Type Flip-Flop

• See 74F50728 for synchronizing cascaded D-Type Flip-Flop

• See 74F50729 for synchronizing Dual D-Type Flip-Flop with Edge-Triggered set and reset


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Part name(s)' : 74ALS109A 74ALS109AN 74ALS109AD
Description : Dual J-K Positive Edge-Triggered Flip-Flop ith set and reset
Philips
Philips Electronics

DESCRIPTION
The 74ALS109A is a Dual Positive Edge-Triggered JK-type Flip-Flop featuring indiviDual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input.
The J and K are Edge-Triggered inputs which control the state changes of the Flip-Flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the Positive-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D Flip-Flop by tying J and K inputs together. Although the clock input is level sensitive, the Positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.

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Part name(s)' : SN54LS109A SN54LS109J SN74LS109 SN74LS109D SN74LS109N
Description : Dual JK Positive Edge-Triggered Flip-Flop
Motorola
Motorola => Freescale

Dual JK Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY



The SN54/74LS109A consists of two high speed completely independent transition clocked JKFlip-Flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D Flip-Flop by simply connecting the J and Kpins together.



 


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Part name(s)' : 54LS74 74LS74A 74LS74J 74LS74N SN54LS74J SN74LS74D SN74LS74N
Description : Dual D-Type Positive-Edge-Triggered Flip-FlopS WITH PRESET AND CLEAR
Motorola
Motorola => Freescale

Dual D-Type Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY



TheSN54/74LS74A Dual Edge-Triggered Flip-Flop utilizesSchottky TTL circuitryto produce high speed D-Type Flip-Flops. Each Flip-Flop hasindiviDual clear and set inputs, and also complementary Q and Qoutputs.



Informationat input D is transferred to the Q output on thePositive-going edgeof the clock pulse. Clock triggering occursat a voltage level of the clock pulseand is not directly related to the transition time of the Positive-going pulse.When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.




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