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Part Name(s) : 74ALS74 Fairchild
Fairchild Semiconductor
Description : Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear View

General Description

The DM74ALS74A contains two independent positive edge-triggered Flip-Flops. Each Flip-Flop has indiviDual D, clock, Clear and Preset inputs, and also complementary Q and Q outputs.

Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.

Asynchronous Preset and Clear inputs will set or Clear Q output respectively upon the application of low level signal.



Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full temperature and VCC range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally and pin-for-pin compatible with Schottky and LS TTL counterpart

■ Improved AC performance over LS74 at approximately half the power



 


Part Name(s) : DM74AS74 DM74AS74M DM74AS74MX DM74AS74N DM74AS74SJX Fairchild
Fairchild Semiconductor
Description : Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear View

General Description

The AS74 is a Dual edge-triggered Flip-Flops. Each Flip-Flop has indiviDual D, clock, Clear and Preset inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.



Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full temperature and VCC range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally and pin-for-pin compatible with Schottky and LS TTL counterpart

■ Improved AC performance over S74 at approximately half the power


Part Name(s) : 54LS74 74LS74A 74LS74J 74LS74N SN54LS74J SN74LS74D SN74LS74N Motorola
Motorola => Freescale
Description : Dual D-Type Positive-Edge-Triggered Flip-FlopS with Preset and Clear View

Dual D-Type POSITIVE EDGE-TRIGGERED Flip-Flop LOW POWER SCHOTTKY



TheSN54/74LS74A Dual edge-triggered Flip-Flop utilizesSchottky TTL circuitryto produce high speed D-Type Flip-Flops. Each Flip-Flop hasindiviDual Clear and set inputs, and also complementary Q and Qoutputs.



Informationat input D is transferred to the Q output on thepositive-going edgeof the clock pulse. Clock triggering occursat a voltage level of the clock pulseand is not directly related to the transition time of the positive-going pulse.When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.




Part Name(s) : DM74LS109A DM74LS109AM DM74LS109AN DM74LS109AMX Fairchild
Fairchild Semiconductor
Description : Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs View

General Description
This device contains two independent Positive-Edge-Triggered J-K Flip-Flops with complementary outputs. The J and K data is accepted by the Flip-Flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the Preset or Clear inputs will set or reset the outputs regard less of the logic levels of the other inputs.


Part Name(s) : SN54LS74AJ SN74LS74A SN74LS74AD SN74LS74AN SN54LS74A Motorola
Motorola => Freescale
Description : Dual D-Type POSITIVE EDGE-TRIGGERED Flip-Flop LOW POWER SCHOTTKY View

Dual D-Type POSITIVE EDGE-TRIGGERED Flip-Flop

The SN54/74LS74A Dual edge-triggered Flip-Flop utilizes Schottky TTL circuitry to produce high speed D-Type Flip-Flops. Each Flip-Flop has indiviDual Clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

Part Name(s) : DM74AS74 DM74AS74M DM74AS74N National-Semiconductor
National ->Texas Instruments
Description : Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear View

General Description

The AS74 is a Dual edge-triggered Flip-Flops. Each Flip-Flop has indiviDual D, clock, Clear and Preset inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.



Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full temperature and VCC range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally and pin-for-pin compatible with Schottky and LS TTL counterpart

■ Improved AC performance over S74 at approximately half the power


Part Name(s) : CD74ACT74-Q1 CD74ACT74QM96G4Q1 CD74ACT74QM96Q1 TI
Texas Instruments
Description : Dual Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset View

description/ordering information

The CD74ACT74 Dual Positive-Edge-Triggered device is a D-Type Flip-Flop.

A low level at the Preset (PRE) or Clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.



• Qualified for Automotive Applications

• Inputs Are TTL-Voltage Compatible

• Speed of Bipolar F, AS, and S, with Significantly Reduced Power Consumption

• Balanced Propagation Delays

• ±24-mA Output Drive Current

   − Fanout to 15 F Devices

• SCR-Latchup-Resistant CMOS Process and Circuit Design



 


Part Name(s) : SN74ALVC74 SN74ALVC74D SN74ALVC74DGV SN74ALVC74PW TI
Texas Instruments
Description : Dual Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset View

description
This Dual Positive-Edge-Triggered D-Type Flip-Flop is designed for 1.65-V to 3.6-V VCC operation.

● EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
● Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages

Part Name(s) : SN54109 SN54109J SN54109W SN54LS109A SN54LS109AFK SN54LS109AJ SN54LS109AW SN74109 SN74109N SN74LS109A TI
Texas Instruments
Description : Dual J-K Positive-Edge-Triggered Flip-FlopS with Preset and Clear View

Dual J-K Positive-Edge-Triggered Flip-FlopS with Preset and Clear

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