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Motorola
Motorola => Freescale
Description : Dual JK Positive Edge-Triggered Flip-Flop

Dual JK Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY



The SN54/74LS109A consists of two high speed completely independent transition clocked JK Flip-Flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D Flip-Flop by simply connecting the J and Kpins together.


Description : Dual JK Positive Edge-Triggered Flip-Flop

Dual JK Positive Edge-Triggered Flip-Flop

Motorola
Motorola => Freescale
Description : Dual JK Positive Edge-Triggered Flip-Flop

Dual JK Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY



The SN54/74LS109A consists of two high speed completely independent transition clocked JKFlip-Flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D Flip-Flop by simply connecting the J and Kpins together.



 


AVG
AVG Semiconductors=>HITEK
Description : Dual JK Negative Edge-Triggered Flip-Flop

Dual JK Negative Edge-Triggered Flip-Flop

Description : Dual JK NEGATIVE Edge-Triggered Flip-Flop

Dual JK Negative Edge-Triggered Flip-Flop

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK Flip-Flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D Flip-Flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

Description : Dual JK NEGATIVE Edge-Triggered Flip-Flop

Dual JK NEGATIVE Edge-Triggered Flip-Flop LOW POWER SCHOTTKY



The SN54/74LS107A is a Dual JK Flip-Flop with indiviDual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 /74LS107A is the same as the SN54/74LS73A but has corner power pins.



 


Philips
Philips Electronics
Description : Dual J-K Positive Edge-Triggered Flip-Flop ith set and reset

DESCRIPTION
The 74ALS109A is a Dual Positive Edge-Triggered JK-type Flip-Flop featuring indiviDual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input.
The J and K are Edge-Triggered inputs which control the state changes of the Flip-Flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the Positive-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D Flip-Flop by tying J and K inputs together. Although the clock input is level sensitive, the Positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.

Motorola
Motorola => Freescale
Description : Dual D-TYPE Positive Edge-Triggered Flip-Flop LOW POWER SCHOTTKY

Dual D-TYPE Positive Edge-Triggered Flip-Flop

The SN54/74LS74A Dual Edge-Triggered Flip-Flop utilizes Schottky TTL circuitry to produce high speed D-type Flip-Flops. Each Flip-Flop has indiviDual clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the Positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the Positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

Philips
Philips Electronics
Description : Synchronizing cascaded Dual Positive Edge-Triggered D-type Flip-Flop

DESCRIPTION

The 74F50728 is a cascaded Dual Positive edge–triggered D–type featuring indiviDual data, clock, set and reset inputs; also true and complementary outputs.



FEATURES

• Metastable immune characteristics

• Output skew less than 1.5ns

• See 74F5074 for synchronizing Dual D-type Flip-Flop

• See 74F50109 for synchronizing Dual J–K Positive Edge-Triggered Flip-Flop

• See 74F50729 for synchronizing Dual Dual D-type Flip-Flop with Edge-Triggered set and reset

• Industrial temperature range available (–40°C to +85°C)



 


Motorola
Motorola => Freescale
Description : Dual JK NEGATIVE Edge-Triggered Flip-Flop

Dual JK NEGATIVE Edge-Triggered Flip-Flop

The SN54 /74LS113A offers indiviDual J, K, set, and clock inputs. These monolithic Dual Flip-Flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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