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Part Name(s) : DV74AC112 DV74AC112N DV74AC112D AVG
AVG Semiconductors=>HITEK
Description : Dual JK Negative Edge-triggered flip-flop View

Dual JK Negative Edge-triggered flip-flop

Part Name(s) : 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV107PWDH Philips
Philips Electronics
Description : Dual JK flip-flop with reset; negative-edge trigger View

DESCRIPTION

The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107.

The 74LV107 is a Dual negative-edge triggered JK-type flip-flop featuring indiviDual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.



FEATURES

• Wide operating: 1.0 to 5.5 V

• Optimized for low voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C

• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C

• Output capability: standard

• ICC category: flip-flops



 


Part Name(s) : 74HC 74HC109 74HCT109 74HC/HCT109 Philips
Philips Electronics
Description : Dual JK flip-flop with set and reset; positive-edge trigger View

GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT109 are Dual positive-edge triggered, JK flip-flops with indiviDual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• J, K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Output capability: standard
• ICC category: flip-flops

Part Name(s) : 74HC107 74HCT107 74HC107D 74HCT107D 74HC107DB 74HC107PW NXP
NXP Semiconductors.
Description : Dual JK flip-flop with reset; negative-edge trigger View

General description
The 74HC107; 74HCT107 is a Dual negative edge triggered JK flip-flop featuring indiviDual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
   
Features and benefits
■ Complies with JEDEC standard no. 7A
■ Input levels:
    ◆ The 74HC107: CMOS levels
    ◆ The 74HCT107: TTL levels
■ ESD protection:
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from -40°C to +85°C and from -40°C to +125°C
   


Part Name(s) : 74HC107 74HC107D 74HC107DB 74HC107N 74HC107PW 74HC107U 74HCT107 74HCT107D 74HCT107DB 74HCT107N Philips
Philips Electronics
Description : Dual JK flip-flop with reset; negative-edge trigger View

GENERAL DESCRIPTION

The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT107 are Dual negative-edge triggered JK-type flip-flops featuring indiviDual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) is an asynchronous active LOW input.

When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.



FEATURES

• Output capability: standard

• ICC category: flip-flops



 


Part Name(s) : MC74AC113 MC74ACT113 MC74AC113N MC74ACT113N MC74AC113D MC74ACT113D Motorola
Motorola => Freescale
Description : Dual JK NEGATIVE EDGE-triggerED flip-flop View

Dual JK Negative Edge-triggered flip-flop

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

Part Name(s) : MC74AC112 MC74AC112D MC74AC112N MC74ACT112 MC74ACT112D MC74ACT112N ON1165 Motorola
Motorola => Freescale
Description : Dual JK NEGATIVE EDGE-triggerED flip-flop View

Dual JK Negative Edge-triggered flip-flop

The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   LOW input to CD (Clear) sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT112 Has TTL Compatible Inputs

Part Name(s) : 74HC107-Q100 74HC107D-Q100 74HC107PW-Q100 74HCT107-Q100 74HCT107D-Q100 NXP
NXP Semiconductors.
Description : Dual JK flip-flop with reset; negative-edge trigger View

General description

The 74HC107-Q100; 74HCT107-Q100 is a Dual negative edge triggered JK flip-flop featuring indiviDual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.



Features and benefits

■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)

♦ Specified from 40 C to +85 C and from 40 C to +125 C

■ Input levels:

♦ For 74HC107-Q100: CMOS level

♦ For 74HCT107-Q100: TTL level

■ Complies with JEDEC standard no. 7A

■ ESD protection:

♦ MIL-STD-883, method 3015 exceeds 2000 V

♦ HBM JESD22-A114F exceeds 2000 V

♦ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

■ Multiple package options



 


Part Name(s) : SN54LS109AJ SN74LS109A SN74LS109AD SN74LS109AN Motorola
Motorola => Freescale
Description : Dual JK POSITIVE EDGE-triggerED flip-flop View

Dual JK POSITIVE EDGE-triggerED flip-flop LOW POWER SCHOTTKY



The SN54/74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by simply connecting the J and Kpins together.


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