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Description : Semirigid, adhesive-lined heat-shrinkable tubing (extended temperature range)

Semirigid, adhesive-lined heat-shrinkable tubing (extended temperature range)

Clear, adhesive-lined ES1000 heat-shrinkable tubing is specifically designed for environmental sealing and electrical insulation of wire splices, terminations, and components where see-through inspection is required.

S1000 tubing has an outer jacket of radiation-crosslinked, semirigid polyolefin. The jacket is mechanically tough, providing strain relief and abrasion protection of wire splices and mechanically sensitive components. The inner layer of the tubing is a unique hot-melt adhesive, specially formulated to seal to most types of commercial wire insulation, and to perform well at an extended temperature range. The thick adhesive forms an effective barrier against fluids and moisture, helping to protect the harness from the effects
of corrosion and water wicking.

Description : Extractor Tool Instruction Sheet Order No. 11-03-0006 (HT2038)

SCOPE
Products: 2.36mm (.093") Diameter, Standard .093" Pin and Socket Crimp Terminals.

FEATURES
■ This Extractor Tool is for the removal of 2.36mm (.093”) Diameter Series pin and socket male and female terminals in both plugs and receptacles.

Description : Extractor Tool Instruction Sheet

SCOPE
Products: 2.36mm (.093") Diameter, Standard .093" Pin and Socket Crimp Terminals and 3.18mm (.125") Diameter HCS-125 Pin and Socket Crimp Terminals

FEATURES
■ This Extractor Tool is for the removal of .093 and HCS-125 Product Series (pin and socket male and female terminals) in both plugs and receptacles.

Part Name(s) : S3P72G9 S3C72G9
Samsung
Samsung
Description : SAM47 Instruction SET

OVERVIEW
The SAM47 Instruction set is specifically designed to support the large register files typically founded in most KS57-series microcontrollers. The SAM47 Instruction set includes 1-bit, 4-bit, and 8-bit Instructions for data manipulation, logical and arithmetic operations, program control, and CPU control. I/O Instructions for peripheral hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the Instruction operand in place of the actual address. Other important features of the SAM47 Instruction set include:

— 1-byte referencing of long Instructions (REF Instruction)
— Redundant Instruction reduction (string effect)
— Skip feature for ADC and SBC Instructions

Instruction operands conform to the operand format defined for each Instruction. Several Instructions have multiple operand formats.

Predefined values or labels can be used as Instruction operands when addressing immediate data. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb, b, and so on. Using Instruction labels can greatly simplify programming and debugging tasks.

Instruction SERT FEATURES
In this section, the following SAM47 Instruction set features are described in detail:
Instruction reference area
Instruction redundancy reduction
— Flexible bit manipulation
— ADC and SBC Instruction skip condition

MOLEX11
Molex Connectors
Description : J5800-001 INSERTION Tool PRODUCT SPECIFICATION

Description
This Tool is an Insertion Tool for the crimp terminal of Molex.
Please take the time to read attached the operating manual (IS-0004) of Insertion Tool, making sure you understand the operating procedures described it before attempting to operate this Tool.

Specifications
1) Tool name: J5800-001 Insertion Tool
2) Tool number: J5800-001
3) Outer dimensions and weight: 105 (width) x 25 (depth) x 10 (thickness) mm, Approx. 20gf
4) Management method: Please confirm that the terminal is locked surely with pulling
   the wire lightly after inserting the terminal.
5) Applicable housing and terminal: 5025 Mini-Fit Connector

Description : Extractor Tool for 1.57mm (.062") Diameter, Standard .062" Pin and Socket Crimp Terminals

SCOPE
    Products: 1.57mm (.062") Diameter, Standard .062" Pin and Socket Crimp Terminals.

FEATURES
■ This Extractor Tool is for the removal of 1.57mm (.062") Diameter Series pin and socket male and female terminals in both plugs and receptacles.

Part Name(s) : PM5313 PM5313-BI
PMC-Sierra
PMC-Sierra
Description : SONET/SDH PAYLOAD Extractor/ALIGNER FOR 622 MBIT/S

DESCRIPTION
The PM5313 SONET/SDH PAYLOAD Extractor/ALIGNER (SPECTRA-622) terminates the transport and path overhead of STS-12 (STM-4/AU3 or STM- 4/AU4) and STS-12c (STM-4-4c) streams at 622.08 Mbit/s. The SPECTRA-622 implements significant functions for a SONET/SDH compliant line interface, as well as DS3 mapping.

FEATURES
General
• MoNo.ithic SONET/SDH PAYLOAD Extractor/ALIGNER for use in STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) interface applications, operating at serial interface speeds of up to 622.08 Mbit/s.
• Provides integrated clock and data recovery and clock synthesis for direct connection to optical modules.
• Supports a duplex byte-serial 77.76 Mbyte/s STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired.
• Supports clock recovery bypass for use in applications where external clock recovery is desired.
• Complies with Bellcore GR-253-CORE jitter tolerance (1995 issue), jitter transfer and intrinsic jitter criteria.
• Provides control circuitry to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
• Provides termination for SONET Section and Line, SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of twelve STS-1 (STM-0/AU3) paths, four STS-3/3c (STM-1/AU3/AU4) paths or a single STS-12c (STM-4-4c) path.
• De-multiplexes an STM-4 receive stream to four STM-1 Telecom DROP bus streams.
• Multiplexes four STM-1 Telecom ADD bus streams to an STM-4 transmit stream.
• Maps twelve STS-1 (STM-0/AU3) payloads, four STS-3/3c (STM-1/AU3/AU4) payloads or a single STS-12c (STM-4-4c) payload to system timing reference, accommodating plesiochroNo.s timing offsets between the references through pointer processing.
• Maps twelve DS3 bit streams into an STS-12 (STM-4/AU3) frame.
• Provides Time Slot Interchange (TSI) function at the Telecom ADD and DROP buses for grooming twelve STS-1 (STM-0/AU3) paths or four STS-3/3c (STM-1/AU3/AU4) paths.
• Supports line loopback from the line side receive stream to the transmit stream and diagNo.tic loopback from a Telecom ADD bus interface to a Telecom DROP bus interface.
• Supports OC-48(STM-16) applications by providing parallel receive and transmit line side ports used to connect to front-end OC-48 devices.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible.
• Industrial temperature range (-40°C to +85°C).
• 520 pin Super BGA package.

APPLICATIONS
• SONET/SDH Add Drop Multiplexers
• SONET/SDH Terminal Multiplexers
• SONET/SDH Line Multiplexers
• SONET/SDH Cross Connects
• SONET/SDH Test Equipment
• Switches and Hubs
• Routers

Description : PIC18F87J50 Family Silicon Errata and Data Sheet Clarification

The PIC18F87J50 family devices that you have received conform functionally to the current Device Data Sheet (DS39775B), except for the aNo.alies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
The errata described in this document will be addressed in future revisions of the PIC18F87J50 family silicon.
Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues.
The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation Tools, which are available at the Microchip corporate web site (www.microchip.com).

For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3:
1. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box.
3. Select the MPLAB hardware Tool (Debugger>Select Tool).
4. Perform a “Connect” operation to the device (Debugger>Connect). Depending on the devel opment Tool used, the part number and Device Revision ID value appear in the Output window.

Description : Clock-Tunable, Quad Second Order, Filter Building Blocks

DESCRIPTION
The LTC®1068 product family consists of four moNo.ithic clock-tunable filter building blocks. Each product contains four matched, low No.se, high accuracy 2nd Order switched-capacitor filter sections. An external clock tunes the center frequency of each 2nd Order filter section. The LTC1068 products differ only in their clock-to-center frequency ratio. The clock-to-center frequency ratio is set to 200:1 (LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or 25:1 (LTC1068-25). External resistors can modify the clock-to-center frequency ratio. High performance, quad 2nd Order, dual 4th Order or 8th Order filters can be designed with an LTC1068 family product. Designing filters with an LTC1068 product is fully supported by FilterCADTM filter design software for Windows®.

FEATURES
■ Four Identical 2nd Order Filter Sections in an SSOP Package
■ 2nd Order Section Center Frequency Error: ±0.3% Typical and ±0.8% Maximum
■ Low No.se per 2nd Order Section, Q ≤ 5:
   LTC1068-200 50µVRMS, LTC1068 50µVRMS
   LTC1068-50 75µVRMS, LTC1068-25 90µVRMS
■ Low Power Supply Current: 4.5mA, Single 5V, LTC1068-50
■ Operation with ±5V Power Supply, Single 5V Supply or Single 3.3V Supply

APPLICATIONS
■ Lowpass or Highpass Filters:
   LTC1068-200, 0.5Hz to 25kHz; LTC1068, 1Hz to
   50kHz; LTC1068-50, 2Hz to 50kHz; LTC1068-25,
   4Hz to 200kHz
■ Bandpass or Bandreject (No.ch) Filters:
   LTC1068-200, 0.5Hz to 15kHz; LTC1068, 1Hz to
   30kHz; LTC1068-50, 2Hz to 30kHz; LTC1068-25,
   4Hz to 140kHz

Description : Clock-Tunable, Quad Second Order, Filter Building Blocks

DESCRIPTION
The LTC®1068 product family consists of four moNo.ithic clock-tunable filter building blocks. Each product contains four matched, low No.se, high accuracy 2nd Order switched-capacitor filter sections. An external clock tunes the center frequency of each 2nd Order filter section. The LTC1068 products differ only in their clock-to-center frequency ratio. The clock-to-center frequency ratio is set to 200:1 (LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or 25:1 (LTC1068-25). External resistors can modify the clock-to-center frequency ratio. High performance, quad 2nd Order, dual 4th Order or 8th Order filters can be designed with an LTC1068 family product. Designing filters with an LTC1068 product is fully supported by FilterCADTM filter design software for Windows®.

FEATURES
■ Four Identical 2nd Order Filter Sections in an SSOP Package
■ 2nd Order Section Center Frequency Error: ±0.3% Typical and ±0.8% Maximum
■ Low No.se per 2nd Order Section, Q ≤ 5:
   LTC1068-200 50µVRMS, LTC1068 50µVRMS
   LTC1068-50 75µVRMS, LTC1068-25 90µVRMS
■ Low Power Supply Current: 4.5mA, Single 5V, LTC1068-50
■ Operation with ±5V Power Supply, Single 5V Supply or Single 3.3V Supply

APPLICATIONS
■ Lowpass or Highpass Filters:
   LTC1068-200, 0.5Hz to 25kHz; LTC1068, 1Hz to
   50kHz; LTC1068-50, 2Hz to 50kHz; LTC1068-25,
   4Hz to 200kHz
■ Bandpass or Bandreject (No.ch) Filters:
   LTC1068-200, 0.5Hz to 15kHz; LTC1068, 1Hz to
   30kHz; LTC1068-50, 2Hz to 30kHz; LTC1068-25,
   4Hz to 140kHz

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