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Part Name(s) : HD74LS174 HD74LS174FPEL HD74LS174P HD74LS174RPEL HD74LS175 HD74LS175FPEL HD74LS175P HD74LS175RPEL Renesas
Renesas Electronics
Description : Hex / Quadruple D-Type Flip-Flops (with Clear) View

Hex / Quadruple D-Type Flip-Flops (with Clear)



These positive-edge-triggered Flip-Flops utilize TTL circuitry toimplement D-Type flip-flop logic. All have a direct

Clear input, and the HD74LS175 features complementary outputs from each Flip-Flops. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.



 


Part Name(s) : 74LS174 74LS175 DM74LS174 DM74LS174M DM74LS174MX DM74LS174N DM74LS174SJ DM74LS174SJX DM74LS175 DM74LS175M Fairchild
Fairchild Semiconductor
Description : Hex/Quad D-Type Flip-Flops with Clear View

General Description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-Type flip-flop logic. All have a direct Clear input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require ments is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a partic ular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ DM74LS174 contains six Flip-Flops with single-rail outputs
■ DM74LS175 contains four Flip-Flops with double-rail outputs
■ Buffered clock and direct Clear inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 14 mW

Part Name(s) : DM74S174 DM74S174N DM74S175 DM74S175N Fairchild
Fairchild Semiconductor
Description : Hex/Quad D Flip-Flop with Clear View

General Description

These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-Type flip-flop logic. All have a direct Clear input, and the quad (DM74S175) versions feature comple mentary outputs from each flip-flop.



Features

■DM74S174 contain six Flip-Flops with single-rail outputs.

■DM74S175 contain four Flip-Flops with double-rail outputs.

■Buffered clock and direct Clear inputs

■Individual data input to each flip-flop

■Applications include:

   Buffer/storage registers

   Shift registers

   Pattern generators

■Typical clock frequency 110 MHz

■Typical power dissipation per flip-flop 75mW


Part Name(s) : SN54AS175A SN54AS175AJ SN74AS175A SN74AS175AD SN74AS175AN SN54AS175AFK TI
Texas Instruments
Description : Hex/QuadRUPLE D-Type Flip-Flops with Clear View

description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-Type flip-flop logic.

• ′ALS174 and ′AS174 Contain Six Flip-Flops
   with Single-Rail Outputs
• ′ALS175 and ′AS175A Contain Four
   Flip-Flops with Double-Rail Outputs
• Buffered Clock and Direct-Clear Inputs
• Applications Include:
   Buffer/Storage Registers
   Shift Registers
   Pattern Generators
• Fully Buffered Outputs for Maximum
   Isolation From External Disturbances
   (′AS Only)
• Package Options Include Plastic
   Small-Outline (D) Packages, Ceramic Chip
   Carriers (FK), and Standard Plastic (N) and
   Ceramic (J) 300-mil DIPs


Part Name(s) : 54LS174 54LS174DMQB 54LS174FMQB 54LS174LMQB 54LS175 54LS175DMQB 54LS175FMQB 54LS175LMQB 74LS174 74LS175 National-Semiconductor
National ->Texas Instruments
Description : Hex/Quad D Flip-Flops with Clear View

General Description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-Type flip-flop logic. All have a direct Clear input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require ments is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

Features
■ LS174 contains six Flip-Flops with single-rail outputs
■ LS175 contains four Flip-Flops with double-rail outputs
■ Buffered clock and direct Clear inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 14 mW
■ Alternate Military/Aerospace device (54LS174, 54LS175) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.

Part Name(s) : MM74HC174 MM74HC174M MM74HC174MTC MM74HC174MTCX MM74HC174MX MM74HC174N MM74HC174SJ MM74HC174SJX Fairchild
Fairchild Semiconductor
Description : Hex D-Type Flip-Flops with Clear View

General Description

The MM74HC174 edge triggered Flip-Flops utilize advanced silicon-gate CMOS technology to implement D-Type flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave Flip-Flops with a common clock and common Clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The Clear input when LOW, sets all outputs to a low state.

Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground.



Features

■ Typical propagation delay: 16 ns

■ Wide operating voltage range: 2–6V

■ Low input current: 1 µA maximum

■ Low quiescent current: 80 µA (74HC Series)

■ Output drive: 10 LSTTL loads



 


Part Name(s) : SN54LS171 SN74LS171 SN54LS171J SN54LS171W SN54LS171FK SN74LS171D SN74LS171N TI
Texas Instruments
Description : QUADRUPLE D-Type Flip-Flops with Clear View

QUADRUPLE D-Type Flip-Flops with Clear

Part Name(s) : DM74174 54174DMQB 54174FMQB 54175DMQB 54175FMQB DM54174J DM54174W DM54175J DM54175W DM74174 Fairchild
Fairchild Semiconductor
Description : Hex/Quad D-Type Flip-Flop with Clear View

General Description
These positive-edge triggered Flip-Flops utilize TTL circuitry to implement D-Type flip-flop logic. All have a direct Clear input.
Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ Contains six Flip-Flops with single-rail outputs
■ Buffered clock and direct Clear inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 38 mW

Part Name(s) : MM74HC273 MM74HC273WM MM74HC273SJ MM74HC273MTC MM74HC273WMX MM74HC273SJX MM74HC273MTCX MM74HC273N ON-Semiconductor
ON Semiconductor
Description : Octal D-Type Flip-Flops with Clear View

General Description
The MM74HC273 edge triggered Flip-Flops utilize advanced silicon-gate CMOS technology to implement D-Type Flip-Flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave Flip-Flops with a common clock and common Clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The Clear input when LOW, sets all outputs to a low state.

Features
■ Typical propagation delay: 18 ns
■ Wide operating voltage range
■ Low input current: 1 μA maximum
■ Low quiescent current: 80 μA (74 Series)
■ Output drive: 10 LS-TTL loads

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