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Part Name(s) : SL4541BD SL4541BN SL4541B System-Logic
System Logic Semiconductor
Description : Programmable Timer High-Performance Silicon-Gate CMOS View

The SL4541 Programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitons and can also be reset via the MASTER RESET input.

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 mA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

Part Name(s) : MACH211SP-10 MACH211SP-10JC MACH211SP-10VC MACH211SP-12 MACH211SP-12JC MACH211SP-12VC MACH211SP-14 MACH211SP-15 MACH211SP-15JC MACH211SP-15VC ETC
Unspecified
Description : High-Performance EE CMOS In-System Programmable Logic View

[VANTIS]

GENERAL DESCRIPTION
The MACH211SP is a member of Vantis’ High-Performance EE CMOS MACH 1 & 2 families. This device has approximately six times the Logic macrocell capability of the popular PALCE22V10 without loss of speed.

DISTINCTIVE CHARACTERISTICS
◆ JTAG-Compatible, 5-V In-System programming
◆ 44 Pins in PLCC and TQFP
◆ 64 Macrocells
◆ 7.5 ns tPD Commercial, 10 ns tPD Industrial
◆ 133 MHz fCNT
◆ 32 I/Os; 2 dedicated inputs/clocks
◆ 64 Flip-flops; 2 clock choices
◆ 4 “PALCE26V16” blocks with buried macrocells
◆ Speed Locking™ for guaranteed fixed timing
◆ Bus-Friendly™ Inputs and I/Os
◆ Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)
Programmable power-down mode

Part Name(s) : ATV750BL-25JI19 Atmel
Atmel Corporation
Description : High-Speed UV-Erasable Programmable Logic Device View

Description

The ATV750B(L) is twice as powerful as most other 24-pin Programmable Logic devices. Increased product terms, sum terms, flip-flops and output Logic configurations translate into more usable gates. High-speed Logic and uniform, predictable delays guarantee fast In-System Performance.



 


Part Name(s) : TIBPAL22V10-5C TIBPAL22V10-5CFN TI
Texas Instruments
Description : High-Performance IMPACT-XL™ Programmable ARRAY Logic CIRCUIT View

description

The TIBPAL22V10-5C is a Programmable array Logic device featuring High speed and functional equivalency when compared to presently available devices. The TIBPAL22V10-5C is implemented with the familiar sum-of-products (AND-OR) Logic structure featuring Programmable output Logic macrocells. These IMPACT-XL circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, High-Performance substitutes for conventional TTL Logic.

This device contains up to 22 inputs and 10 outputs. It incorporates the unique capability of defining and programming the architecture of each output on an individual basis. Outputs can be registered or nonregistered and inverting or noninverting as shown in the output Logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms.



High-Performance Operation:

   fmax (External Feedback) . . . 117 MHz

   Propagation Delay . . . 5 ns Max

• Increased Logic Power – Up to 22 Inputs and 10 Outputs

• Increased Product Terms – Average of 12 Per Output

• Variable Product Term Distribution Allows More Complex Functions to Be Implemented

• Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control

• Power-Up Clear on Registered Outputs

• TTL-Level Preload for Improved Testability

• Extra Terms Provide Logical Synchronous

   Set and Asynchronous Reset Capability

• Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses

• AC and DC Testing Done at the Factory

   Utilizing Special Designed-In Test Features

• JEDEC Approved Revolutionary Power and Ground Pinout for 28-Pin Chip Carrier Reduces Cross Talk and Ground Bounce

• JEDEC File Compatibility Allows Previous ’22V10 Designs to be Programmed Into the TIBPAL22V10-5C Without Modifications



 



Part Name(s) : TIBPAL22V10-10C TIBPAL22V10-10CFN TIBPAL22V10-10CNT TI
Texas Instruments
Description : High-Performance IMPACT-X™ Programmable ARRAY Logic CIRCUITS View

description

The TIBPAL22V10-10C is a Programmable array Logic device featuring High speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) Logic structure featuring the new concept “Programmable Output Logic Macrocell”. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium tungsten fuses to provide reliable, High-Performance substitutes for conventional TTL Logic.

These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output Logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms.



• Second-Generation PLD Architecture

High-Performance Operation:

   fmax (External Feedback) . . . 71 MHz

   Propagation Delay . . . 10 ns Max

• Increased Logic Power – Up to 22 Inputs and 10 Outputs

• Increased Product Terms – Average of 12 Per Output

• Variable Product Term Distribution Allows More Complex Functions to Be Implemented

• Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control

• Power-Up Clear on Registered Outputs

• TTL-Level Preload for Improved Testability

• Extra Terms Provide Logical Synchronous

   Set and Asynchronous Reset Capability

• Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses

• AC and DC Testing Done at the Factory

   Utilizing Special Designed-In Test Features

• Dependable Texas Instruments Quality and Reliability

• Package Options Include Plastic

   Dual-In-Line and Chip Carrier Packages



 


Part Name(s) : TIBPAL22V10-15BC TIBPAL22V10-15BCFN TIBPAL22V10-15BCNT TI
Texas Instruments
Description : High-Performance IMPACT-X™ Programmable ARRAY Logic CIRCUITS View

description

The TIBPAL22V10-15BC is a Programmable array Logic device featuring High speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) Logic structure featuring the new concept “Programmable Output Logic Macrocell”. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, High-Performance substitutes for conventional TTL Logic.

These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output Logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms.



• Second-Generation PLD Architecture

High-Performance Operation:

   fmax (External Feedback) . . . 40 MHz

   Propagation Delay . . . 15 ns Max

• Increased Logic Power – Up to 22 Inputs and 10 Outputs

• Increased Product Terms – Average of 12 per Output

• Variable Product Term Distribution Allows More Complex Functions to Be Implemented

• Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control

• Power-Up Clear on Registered Outputs

• TTL-Level Preload for Improved Testability

• Extra Terms Provide Logical Synchronous

   Set and Asynchronous Reset Capability

• Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses

• AC and DC Testing Done at the Factory

   Utilizing Special Designed-In Test Features

• Dependable Texas Instruments Quality and Reliability

• Package Options Include Plastic

   Dual-In-Line and Chip Carrier Packages



 


Part Name(s) : M4-192 M4-32/32-12VI48 M4-64/32-10VC48 M4-64/32-10VI48 M4-64/32-12VC48 M4-64/32-12VI48 M4-64/32-14VI48 M4-64/32-15VC48 M4-64/32-18VI48 M4-64/32-7VC48 Lattice
Lattice Semiconductor
Description : MACH 4 CPLD Family High Performance E2CMOS® In-System Programmable Logic View

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V In-System Programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
High-Performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid Logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM Performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% pin-out retention
High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG In-System programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides High-Performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid Logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for In-System programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

Part Name(s) : M4A3-32/32-7VIM4A3-128/64-7YI M4A5-32/32-7VC48 M4A5-32/32-7VI48 M4A5-64/32-7VI48 Lattice
Lattice Semiconductor
Description : 7ns, 3.3V High Performance E2 CMOS In-System Programmable Logic View

FEATURES

High-Performance, E2CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid Logic designs

— Excellent First-Time-FitTM and refit feature

— SpeedLocking Performance for guaranteed fixed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

— 5.0ns tPD Commercial and 7.5ns tPD Industrial

— 182MHz fCNT

◆ 32 to 512 macrocells; 32 to 768 registers

◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆ Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

Programmable polarity

— Reset/ preset swapping


Part Name(s) : ISPLSI1032-60LGI Lattice
Lattice Semiconductor
Description : In-System Programmable High Density PLD View

Description
The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032/883 features 5-Volt In-System programming and In-System diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the Logic, as well as the interconnect to provide truly reconfigurable systems.

Features
High-DENSITY Programmable Logic
    — High Speed Global Interconnect
    — 6000 PLD Gates
    — 64 I/O Pins, Eight Dedicated Inputs
    — 192 Registers
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Fast Random Logic
    — Security Cell Prevents Unauthorized Copying
High Performance E2CMOS® TECHNOLOGY
    — fmax = 60 MHz Maximum Operating Frequency
    — tpd = 20 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and ReProgrammable
    — Non-Volatile E2CMOS Technology
    — 100% Tested
In-System Programmable
    — In-System Programmable™ (ISP™) 5-Volt Only
    — Increased Manufacturing Yields, Reduced Time-to-Market, and Improved Product Quality
    — Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS
    — Complete Programmable Device Can Combine Glue Logic and Structured Designs
    — Four Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – Logic COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH In-System PROGRAMMING
    — Superior Quality of Results
    — Tightly Integrated with Leading CAE Vendor Tools
    — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
    — PC and UNIX Platforms

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