Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

P/N + Description + Content Search

Search Word's :

Part Name(s) : M4-192 M4-32/32-12VI48 M4-64/32-10VC48 M4-64/32-10VI48 M4-64/32-12VC48 M4-64/32-12VI48 M4-64/32-14VI48 M4-64/32-15VC48 M4-64/32-18VI48 M4-64/32-7VC48 Lattice
Lattice Semiconductor
Description : MACH 4 CPLD Family High Performance E2CMOS® In-System Programmable Logic View

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V In-System Programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
High-Performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid Logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM Performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% pin-out retention
High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG In-System programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides High-Performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid Logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for In-System programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

Part Name(s) : GAL6001 GAL6001B-30LJ GAL6001B-30LP GAL6001B Lattice
Lattice Semiconductor
Description : High Performance E2CMOS FPLA Generic Array Logic View

Description
Using a High Performance E2CMOS technology, Lattice Semiconductor has produced a next-generation Programmable Logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a High degree of functional integration and flexibility in a 24-pin, 300-mil package.

Features
High Performance E2CMOS® TECHNOLOGY
    — 30ns Maximum Propagation Delay
    — 27MHz Maximum Frequency
    — 12ns Maximum Clock to Output Delay
    — TTL Compatible 16mA Outputs
    — UltraMOS® Advanced CMOS Technology
• LOW POWER CMOS
    — 90mA Typical Icc
• E2 CELL TECHNOLOGY
    — Reconfigurable Logic
    — ReProgrammable Cells
    — 100% Tested/100% Yields
    — High Speed Electrical Erasure (<100ms)
    — 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
    — 78 x 64 x 36 FPLA Architecture
    — 10 Output Logic Macrocells
    — 8 Buried Logic Macrocells
    — 20 Input and I/O Logic Macrocells
High-LEVEL DESIGN FLEXIBILITY
    — Asynchronous or Synchronous Clocking
    — Separate State Register and Input Clock Pins
    — Functional Superset of Existing 24-pin PAL®
    and FPLA Devices
• APPLICATIONS INCLUDE:
    — Sequencers
    — State Machine Control
    — Multiple PLD Device Integration

Part Name(s) : GAL6002 GAL6002B GAL6002B-15LP GAL6002B-15LJ GAL6002B-20LP GAL6002B-20LJ Lattice
Lattice Semiconductor
Description : High Performance E2CMOS FPLA Generic Array Logic View

Description
Having an FPLA architecture, the GAL6002 provides superior flexibility in state-machine design. The GAL6002 offers the Highest degree of functional integration, flexibility, and speed currently available in a 24-pin, 300-mil package. E2CMOS technology offers High speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

Features
High Performance E2CMOS® TECHNOLOGY
    — 15ns Maximum Propagation Delay
    — 75MHz Maximum Frequency
    — 6.5ns Maximum Clock to Output Delay
    — TTL Compatible 16mA Outputs
    — UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
    — 90mA Typical Icc
• E2 CELL TECHNOLOGY
    — Reconfigurable Logic
    — ReProgrammable Cells
    — 100% Tested/100% Yields
    — High Speed Electrical Erasure (<100ms)
    — 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
    — 78 x 64 x 36 FPLA Architecture
    — 10 Output Logic Macrocells
    — 8 Buried Logic Macrocells
    — 20 Input and I/O Logic Macrocells
High-LEVEL DESIGN FLEXIBILITY
    — Asynchronous or Synchronous Clocking
    — Separate State Register and Input Clock Pins
    — Functional Superset of Existing 24-pin PAL®
    and FPLA Devices
• APPLICATIONS INCLUDE:
    — Sequencers
    — State Machine Control
    — Multiple PLD Device Integration

Part Name(s) : M4A3-32/32-10VC48 M4A3-32/32-10VI48 M4A3-32/32-12VI48 M4A3-32/32-55VC48 M4A3-32/32-5VC48 M4A3-32/32-7VC48 M4A3-32/32-7VI48 M4A3-64/32-10VC48 M4A3-64/32-10VI48 M4A3-64/32-12VI48 Lattice
Lattice Semiconductor
Description : ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic View

FEATURES

High-Performance, E2CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid Logic designs

    — Excellent First-Time-FitTM and refit feature

    — SpeedLocking Performance for guaranteed fixed timing

    — Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆  High speed

    — 5.0ns tPD Commercial and 7.5ns tPD Industrial

    — 182MHz fCNT

◆ 32 to 512 macrocells; 32 to 768 registers

◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆ Flexible architecture for a wide range of design styles



Part Name(s) : ISPLSI1032-60LGI Lattice
Lattice Semiconductor
Description : In-System Programmable High Density PLD View

Description
The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032/883 features 5-Volt In-System programming and In-System diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the Logic, as well as the interconnect to provide truly reconfigurable systems.

Features
High-DENSITY Programmable Logic
    — High Speed Global Interconnect
    — 6000 PLD Gates
    — 64 I/O Pins, Eight Dedicated Inputs
    — 192 Registers
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Fast Random Logic
    — Security Cell Prevents Unauthorized Copying
High Performance E2CMOS® TECHNOLOGY
    — fmax = 60 MHz Maximum Operating Frequency
    — tpd = 20 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and ReProgrammable
    — Non-Volatile E2CMOS Technology
    — 100% Tested
In-System Programmable
    — In-System Programmable™ (ISP™) 5-Volt Only
    — Increased Manufacturing Yields, Reduced Time-to-Market, and Improved Product Quality
    — Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS
    — Complete Programmable Device Can Combine Glue Logic and Structured Designs
    — Four Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – Logic COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH In-System PROGRAMMING
    — Superior Quality of Results
    — Tightly Integrated with Leading CAE Vendor Tools
    — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
    — PC and UNIX Platforms

Part Name(s) : GAL22V10D-15LJN GAL22V10D-15LJNI GAL22V10D-15LPN GAL22V10D-15LPNI GAL22V10D-20LJI GAL22V10D-20LPI GAL22V10D-5LJN Lattice
Lattice Semiconductor
Description : High Performance E2CMOS PLD Generic Array Logic View

Description

The GAL22V10, at 4ns maximum propagation delay time, combines a High Performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the Highest Performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2 technology offers High speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.



Features

High Performance E2CMOS®TECHNOLOGY

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3.5 ns Maximum from Clock Input to Data Output

— UltraMOS®Advanced CMOS Technology

• ACTIVE PULL-UPS ON ALL PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES

— Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices

• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR

— 90mA Typical Icc on Low Power Device

— 45mA Typical Icc on Quarter Power Device

•E2CELL TECHNOLOGY

— Reconfigurable Logic

— ReProgrammable Cells

— 100% Tested/100% Yields

High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• TEN OUTPUT Logic MACROCELLS

— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION


Part Name(s) : SL4541BD SL4541BN SL4541B System-Logic
System Logic Semiconductor
Description : Programmable Timer High-Performance Silicon-Gate CMOS View

The SL4541 Programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitons and can also be reset via the MASTER RESET input.

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 mA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

Part Name(s) : GAL18V10-10LJ GAL18V10-10LP GAL18V10-15LJ GAL18V10-15LP GAL18V10-20LJ GAL18V10-20LP GAL18V10-7LJ GAL18V10-7LP Lattice
Lattice Semiconductor
Description : High Performance E2CMOS PLD Generic Array Logic View

Description

The GAL18V10, at 7.5 ns maximum propagation delay time, combines a High Performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers High speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.



Features

High Performance E2CMOS®TECHNOLOGY

—7.5 ns Maximum Propagation Delay

—Fmax = 111 MHz

—5.5 ns Maximum from Clock Input to Data Output

—TTL Compatible 16 mA Outputs

—UltraMOS® Advanced CMOS Technology

•LOW POWER CMOS

—75 mA Typical Icc

•ACTIVE PULL-UPS ON ALL PINS

•E2CELL TECHNOLOGY

—Reconfigurable Logic

—ReProgrammable Cells

—100% Tested/100% Yields

High Speed Electrical Erasure (<100ms)

—20 Year Data Retention

•TEN OUTPUT Logic MACROCELLS

—Uses Standard 22V10 Macrocell Architecture

—Maximum Flexibility for Complex Logic Designs

•PRELOAD AND POWER-ON RESET OF REGISTERS

—100% Functional Testability

•APPLICATIONS INCLUDE:

—DMA Control

—State Machine Control

High Speed Graphics Processing

—Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

 


Part Name(s) : 5962-9558701MXC ISPLSI1048C/883 ISPLSI1048C-50LG/883 Lattice
Lattice Semiconductor
Description : In-System Programmable High Density PLD View

Description
The ispLSI 1048C/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD- 883. This military grade device contains 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, two Global Output Enables (GOE), four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Features
High-DENSITY Programmable Logic
    — 8000 PLD Gates
    — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables
    — 288 Registers
    — High-Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
    — Security Cell Prevents Unauthorized Copying
High Performance E2CMOS® TECHNOLOGY
    — fmax = 50 MHz Maximum Operating Frequency
    — tpd = 22 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and ReProgrammable
    — Non-Volatile E2CMOS Technology
    — 100% Tested at Time of Manufacture
In-System Programmable
    — In-System Programmable™ (ISP™) 5-Volt Only
    — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
    — Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD Programmable GATE ARRAYS
    — Complete Programmable Device Can Combine Glue Logic and Structured Designs
    — Four Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – Logic COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH In-System PROGRAMMING
    — Superior Quality of Results
    — Tightly Integrated with Leading CAE Vendor Tools
    — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
    — PC and UNIX Platforms

12345678910 Next



All Rights Reserved© datasheetq.com 2015 - 2020  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]