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System-Logic
System Logic Semiconductor
Description : Dual 4-Stage Binary Ripple Counter High-Performance Silicon-Gate CMOS

Dual 4-Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS

The SL74HC393 is identical in pinout to the LS/ALS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 4-Bit Binary Ripple Counters with parallel outputs from each Counter stage. A¸256 Counter can be obtained by cascading the two Binary Counters.
Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the Counters is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously becaue of internal Ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the SL74HC393.

 • Outputs Directly Interface to CMOS, NMOS, and TTL
 • Operating Voltage Range: 2.0 to 6.0 V
 • Low Input Current: 1.0 μ
 • High Noise Immunity Characteristic of CMOS Devices

System-Logic
System Logic Semiconductor
Description : 14-Stage Ripple-Carry Binary Counter/Divider and Oscillator High-Voltage Silicon-Gate CMOS

14-Stage Ripple-Carry Binary Counter/Divider and Oscillator High-Voltage Silicon-Gate CMOS

The SL4060B consists of an oscillator section and 14 Ripple-carry Binary Counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A RESET input is provided which resets the Counter to the all-Q’s state and disables the oscillator. A high level on the RESET line accomplishes the reset function. All Counter stages are master-slave flip-flops. The state of the Counter is advanced one step in Binary order on the negative transition of OSC In (and OSC Out). Schmitt trigger action on the input-pulse line permits unlimited input-pulse rise and fall times.

 • Operating Voltage Range: 3.0 to 18 V
 • Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
 • Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

SLS
System Logic Semiconductor
Description : Dual 4-Stage Binary Ripple Counter

Dual 4-Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS

The SL74HC393 is identical in pinout to the LS/ALS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 4-Bit Binary Ripple Counters with parallel outputs from each Counter stage. A¸256 Counter can be obtained by cascading the two Binary Counters.
Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the Counters is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously becaue of internal Ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the SL74HC393.

 • Outputs Directly Interface to CMOS, NMOS, and TTL
 • Operating Voltage Range: 2.0 to 6.0 V
 • Low Input Current: 1.0 μ
 • High Noise Immunity Characteristic of CMOS Devices

INTE-ElectronicGRAL
Integral Corp.
Description : DUAL 4-STAGE Binary Ripple Counter High-Performance Silicon-Gate CMOS

The IN74HC393 is identical in pinout to the LS/ALS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 4-Bit Binary Ripple Counters with parallel outputs from each Counter stage. A÷256 Counter can be obtained by cascading the two Binary Counters.
Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the Counters is asynchronous and activehigh. State changes of the Q outputs do not occur simultaneously becaue of internal Ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the IN74HC393.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

IKSEMICON
IK Semicon Co., Ltd
Description : Dual 4-Stage Binary Ripple Counter High-Performance Silicon-Gate CMOS

The IN74HC393A is identical in pinout to the LS/ALS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 4-Bit Binary Ripple Counters with parallel outputs from each Counter stage. A÷256 Counter can be obtained by cascading the two Binary Counters.
Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the Counters is asynchronous and activehigh. State changes of the Q outputs do not occur simultaneously becaue of internal Ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the IN74HC393A.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

ON-Semiconductor
ON Semiconductor
Description : Dual 4-Stage Binary Ripple Counter

Dual 4-Stage Binary Ripple Counter High–Performance Silicon–Gate CMOS

The MC74HC393A is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4–bit Binary Ripple Counters with parallel outputs from each Counter stage. A ÷ 256 Counter can be obtained by cascading the two Binary Counters.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 236 FETs or 59 Equivalent Gates

System-Logic
System Logic Semiconductor
Description : 14 Stage Ripple-Carry Binary Counter/Divider High-Voltage Silicon-Gate CMOS

The SL4020B is Ripple-carry Binary Counter. All Counter stages are master-slave flip-flops. The state of a Counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the Counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.

● Operating Voltage Range: 3.0 to 18 V
● Maximum input current of 1 mA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
● Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

Description : Dual 4-Bit Binary Ripple Counter

GENERAL DESCRIPTION
The 74HC/HCT393 are High-Speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT393 are 4-Bit Binary Ripple Counters with separate clocks (1CP and 2 CP) and master reset (1MR and 2MR) inputs to each Counter. The operation of each half of the “393” is the same as the “93” except no external clock connections are required.
The Counters are triggered by a HIGH-to-LOW transition of the clock inputs. The Counter outputs are internally connected to provide clock inputs to succeeding stages.
The outputs of the Ripple Counter do not change synchronously and should not be used for High-Speed address decoding.
The master resets are active-HIGH asynchronous inputs to each 4-Bit Counter identified by the “1” and “2” in the pin description.
A HIGH level on the nMR input overrides the clock and sets the outputs LOW.

FEATURES
• Two 4-Bit Binary Counters with individual clocks
• Divide-by any Binary module up to 28 in one package
• Two master resets to clear each 4-Bit Counter
   individually
• Output capability: standard
• ICC category: MSI

ON-Semiconductor
ON Semiconductor
Description : Dual 4−Stage Binary Ripple Counter

Dual 4−Stage Binary Ripple Counter High−Performance Silicon−Gate CMOS

The MC54/74HC393 is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit Binary Ripple Counters with parallel outputs from each Counter stage. A ÷ 256 Counter can be obtained by cascading the two Binary Counters.

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 236 FETs or 59 Equivalent Gates

Integral
Integral Corp.
Description : 14-Stage Ripple-Carry Binary Counter/Divider and Oscillator High-Voltage Silicon-Gate CMOS

14-Stage Ripple-Carry Binary Counter/Divider and Oscillator High-Voltage Silicon-Gate CMOS

The IW4060B consists of an oscillator section and 14 Ripple-carry Binary Counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A RESET input is provided which resets the Counter to the all-Q’s state and disables the oscillator. A high level on the RESET line accomplishes the reset function. All Counter stages are master-slave flip-flops. The state of the Counter is advanced one step in Binary order on the negative transition of OSC In (and OSC Out). Schmitt trigger action on the input-pulse line permits unlimited input-pulse rise and fall times.

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply

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