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Part Name(s) : CD54HC4059 CD74HC4059 5962-8944501JA CD54HC4059F3A CD74HC4059E CD74HC4059EE4 CD74HC4059M96 CD74HC4059M96E4 CD74HC4059M96G4 TI
Texas Instruments
Description : High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter View

Description
The ’HC4059 are High-Speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are Divide-by-N down-Counters that can be programmed to divide an input frequency by any number “N” from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-Counter is preset by means of 16 jam inputs.

Features
• Synchronous Programmable÷N Counter N = 3 to 9999 or 15999
• Presettable Down-Counter
• Fully Static Operation
• Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2)
• Master Preset Initialization
• Latchable÷N Output
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL= 30%, NIH= 30% of VCC at VCC= 5V

Applications
• Communications Digital Frequency Synthesizers; VHF, UHF, FM, AM, etc.
• Fixed or Programmable Frequency Division
• “Time Out” Timer for Consumer-Application Industrial Controls

Part Name(s) : 5962-8944501JA CD54HC4059 CD74HC4059 CD74HC4059M96E4 CD74HC4059M96G4 HC4059M CD54HC4059F3A CD74HC4059E CD74HC4059M96 Texas-Instruments
Texas Instruments
Description : High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter View

Description
The ’HC4059 are High-Speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are Divide-by-N down-Counters that can be programmed to divide an input frequency by any number “N” from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-Counter is preset by means of 16 jam inputs.

Features
• Synchronous Programmable ÷N Counter N = 3 to 9999
   or 15999
• Presettable Down-Counter
• Fully Static Operation
• Mode-Select Control of Initial Decade Counting
   Function (÷10, 8, 5, 4, 2)
• Master Preset Initialization
• Latchable ÷N Output
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
   Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
      at VCC = 5V
  
Applications
• Communications Digital Frequency Synthesizers;
   VHF, UHF, FM, AM, etc.
• Fixed or Programmable Frequency Division
• “Time Out” Timer for Consumer-Application Industrial
   Controls

Part Name(s) : HD14522B HD14526B Hitachi
Hitachi -> Renesas Electronics
Description : Programmable Divide-by-N 4-bit Counter View

Programmable Divide-by-N 4-bit Counter

Part Name(s) : 74HC4059 74HC4059D 74HC4059N 74HC4059N3 74HC4059U 74HCT4059 74HCT4059D 74HCT4059N 74HCT4059N3 74HCT4059U Philips
Philips Electronics
Description : Programmable Divide-by-N Counter View

GENERAL DESCRIPTION

The 74HC/HCT4059 are High-Speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT4059 are Divide-by-N Counters which can be programmed to divide an input frequency by any number (n) from 3 to 15 999. There are four operating modes, timer, Divide-by-N, divide-by-10 000 and master preset, which are defined by the mode select inputs (Ka to Kc) and the latch enable input (LE) as shown in the Function table.

The complete Counter consists of a first counting stage, an intermediate counting stage and a fifth counting stage. The first Counter stage consists of four independent flip-flops. Depending on the divide-by-mode, at least one flip-flop is placed at the input of the intermediate stage (the remaining flip-flops are placed at the fifth stage with a place value of thousands). The intermediate stage consists of three cascaded decade Counters, each containing four flip-flops.



FEATURES

• Synchronous Programmable Divide-by-N Counter

• Presettable down Counter

• Fully static operation

• Mode select control of initial decade counting function

   (divide-by-10, 8, 5, 4 and 2)

• Master preset initialization

• Latchable output

• Easily cascadable with other Counters

• Four operating modes:

   timer

   divider-by-n

   divide-by-10 000

   master preset

• Output capability: standard

• ICC category: MSI



 



Part Name(s) : HEF4059B HEF4059BD HEF4059BF HEF4059BN HEF4059BP HEF4059BPB HEF4059BT HEF4059BU Philips
Philips Electronics
Description : Programmable Divide-by-N Counter View

DESCRIPTION

The HEF4059B is a Divide-by-N Counter which can be programmed to divide an input frequency by any number n from 3 to 15 999. The output signal is a one clock-cycle wide pulse and occurs at a rate equal to the input frequency divided by n. The single output (O) has TTL drive capability. The down Counter is preset by means of

16 jam inputs (J1 to J16); continued on next page.


Part Name(s) : MC14569B MC14569BCP MC14569BCPG MC14569BDT MC14569BDW MC14569BDWG MC14569BDWR2 MC14569BDWR2G ON-Semiconductor
ON Semiconductor
Description : Programmable Divide−By−N Dual 4−Bit Binary/BCD Down Counter View

The MC14569B is a Programmable divide−by−N dual 4−bit binary or BCD down Counter constructed with MOS P−Channel and N−Channel enhancement mode devices (complementary MOS) in a monolithic structure.

This device has been designed for use with the MC14568B phase comparator/Counter in frequency synthesizers, phase−locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.



Features

• Speed−up Circuitry for Zero Detection

• Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode

• Can be Cascaded With MC14526B for Frequency Synthesizer Applications

• All Outputs are Buffered

• Schmitt Triggered Clock Conditioning

• Pb−Free Packages are Available*


Part Name(s) : 74LS90 74LS92 74LS93 SN54LS90J SN54LS92J SN54LS93J SN74LS90N SN74LS92D SN74LS92N SN74LS93D Motorola
Motorola => Freescale
Description : DECADE Counter / DIVIDE-BY-TWELVE Counter / 4-BIT BINARY Counter View

The SN54/74LS90, SN54/74LS92 andSN54/74LS93 are High-Speed 4-bitripple type Counters partitioned intotwo sections. Each Counter has a divide-by-twosection andeither a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight(LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs.






1. Low Power Consumption . . . Typically 45 mW

2. High Count Rates . . . Typically 42 MHz

3. Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary

4. Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : 7490 74LS90 74LS90D SN74LS90 SN74LS90DR2 SN74LS90N SN74LS90D SN54LS90J ON-Semiconductor
ON Semiconductor
Description : DECADE Counter; DIVIDE-BY-TWELVE Counter; 4-BIT BINARY Counter View

The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are High-Speed 4-bit ripple type Counters partitioned into two sections. Each Counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 Counters. All of the Counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary
• Input Clamp Diodes Limit High Speed Termination Effects

Part Name(s) : SN54-74LS90 SN54LS90 SN54LS92 SN54LS92J SN54LS93 SN54LS93J SN74LS92 SN74LS92D SN74LS92N SN74LS93 ON-Semiconductor
ON Semiconductor
Description : DECADE Counter; DIVIDE-BY-TWELVE Counter; 4-BIT BINARY Counter View

The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are High-Speed 4-bit ripple type Counters partitioned into two sections. Each Counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 Counters. All of the Counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).



• Low Power Consumption . . . Typically 45 mW

• High Count Rates . . . Typically 42 MHz

• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, Binary

• Input Clamp Diodes Limit High Speed Termination Effects



 


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