FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
- Excellent First-Time-FitTM and refit feature
- SpeedLocking performance for guaranteed fixed timing
- Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
- 7.5ns tPD Commercial and 10ns tPD Industrial
- 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
- D/T registers and latches
- Synchronous or asynchronous mode
- Dedicated input registers
- programmable polarity
- Reset/ preset swapping
GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex programmable logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.
FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and refit feature
— SpeedLockingTM performance for guaranteed fixed timing
— Central, input and output switch matrices
for 100% routability and 100% pin-out retention
◆ High speed
— 7.5ns tPD Commercial and 10ns tPD Industrial
— 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— programmable polarity
— Reset/ preset swapping
◆ Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Bus-FriendlyTM inputs and I/Os
— programmable security bit
— Individual output slew rate control
◆ Advanced E2CMOS process provides High-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 4
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
— LatticePROTM software for in-system programmability support
on PCs and automated test equipment
— Programming support on all major programmers including Data I/O,
BP Microsystems, Advin, and System General
FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and refit feature
— SpeedLocking performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and refit feature
— SpeedLocking performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— programmable polarity
— Reset/ preset swapping
Description
Using a high performance E2CMOS technology, Lattice Semiconductor has produced a next-generation programmable logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a high degree of functional integration and flexibility in a 24-pin, 300-mil package.
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS® Advanced CMOS Technology
• LOW POWER CMOS
— 90mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output logic macrocells
— 8 Buried logic macrocells
— 20 Input and I/O logic macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL®
and FPLA Devices
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
[VANTIS]
GENERAL DESCRIPTION
The MACH211SP is a member of Vantis’ High-performance EE CMOS MACH 1 & 2 families. This device has approximately six times the logic macrocell capability of the popular PALCE22V10 without loss of speed.
DISTINCTIVE CHARACTERISTICS
◆ JTAG-Compatible, 5-V in-system programming
◆ 44 Pins in PLCC and TQFP
◆ 64 macrocells
◆ 7.5 ns tPD Commercial, 10 ns tPD Industrial
◆ 133 MHz fCNT
◆ 32 I/Os; 2 dedicated inputs/clocks
◆ 64 Flip-flops; 2 clock choices
◆ 4 “PALCE26V16” blocks with buried macrocells
◆ Speed Locking™ for guaranteed fixed timing
◆ Bus-Friendly™ Inputs and I/Os
◆ Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)
◆ programmable power-down mode
GENERAL DESCRIPTION
The MACH111 is a member of Vantis’ High-performance EE CMOS MACH 1 & 2 families. This device has approximately three times the logic macrocell capability of the popular PALCE22V10 without loss of speed.
DISTINCTIVE CHARACTERISTICS
◆ 44 Pins in PLCC and TQFP
◆ 32 macrocells
◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial
◆ 182 MHz fCNT
◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
◆ 32 Flip-flops; 4 clock choices
◆ 2 “PALCE26V16” blocks
◆ SpeedLocking™ for guaranteed fixed timing
◆ Bus-Friendly™ Inputs and I/Os
◆ Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12)
◆ programmable power-down mode
◆ Safe for mixed supply voltage system designs
◆ Pin-compatible with the MACH211
GENERAL DESCRIPTION
The MACH® 1 & 2 families from Lattice/Vantis offer High-performance, low cost Complex programmable logic Devices (CPLDs), addressing the growing need for speed in networking, telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns tPD and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
FEATURES
◆ High-performance electrically-erasable CMOS PLD families
◆ 32 to 128 macrocells
◆ 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
◆ SpeedLocking™ – guaranteed fixed timing up to 16 product terms
◆ Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD
◆ Configurable macrocells
— programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
◆ JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
◆ Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
◆ Safe for mixed supply voltage system designs
◆ Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
◆ programmable power-down mode results in power savings of up to 75%
◆ Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
◆ Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO®) software for in-system programmability support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
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