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FEATURES

◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid logic designs

    - Excellent First-Time-FitTM and refit feature

    - SpeedLocking performance for guaranteed fixed timing

    - Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆ High speed

    - 7.5ns tPD Commercial and 10ns tPD Industrial

    - 111.1MHz fCNT

◆ 32 to 256 macrocells; 32 to 384 registers

◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages

◆ Flexible architecture for a wide range of design styles

    - D/T registers and latches

    - Synchronous or asynchronous mode

    - Dedicated input registers

    - programmable polarity

    - Reset/ preset swapping

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% pin-out retention
◆ High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — programmable polarity
   — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG in-system programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides High-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for in-system programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

FEATURES

◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid logic designs

    — Excellent First-Time-FitTM and refit feature

    — SpeedLocking performance for guaranteed fixed timing

    — Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆  High speed

    — 5.0ns tPD Commercial and 7.5ns tPD Industrial

    — 182MHz fCNT

◆ 32 to 512 macrocells; 32 to 768 registers

◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆ Flexible architecture for a wide range of design styles

FEATURES

◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families

◆ Flexible architecture for rapid logic designs

— Excellent First-Time-FitTM and refit feature

— SpeedLocking performance for guaranteed fixed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆ High speed

— 5.0ns tPD Commercial and 7.5ns tPD Industrial

— 182MHz fCNT

◆ 32 to 512 macrocells; 32 to 768 registers

◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

◆ Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— programmable polarity

— Reset/ preset swapping

[VANTIS]

GENERAL DESCRIPTION
The MACH211SP is a member of Vantis’ High-performance EE CMOS MACH 1 & 2 families. This device has approximately six times the logic macrocell capability of the popular PALCE22V10 without loss of speed.

DISTINCTIVE CHARACTERISTICS
◆ JTAG-Compatible, 5-V in-system programming
◆ 44 Pins in PLCC and TQFP
◆ 64 Macrocells
◆ 7.5 ns tPD Commercial, 10 ns tPD Industrial
◆ 133 MHz fCNT
◆ 32 I/Os; 2 dedicated inputs/clocks
◆ 64 Flip-flops; 2 clock choices
◆ 4 “PALCE26V16” blocks with buried macrocells
◆ Speed Locking™ for guaranteed fixed timing
◆ Bus-Friendly™ Inputs and I/Os
◆ Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)
◆ programmable power-down mode

Description
Having an FPLA architecture, the GAL6002 provides superior flexibility in state-machine design. The GAL6002 offers the highest degree of functional integration, flexibility, and speed currently available in a 24-pin, 300-mil package. E2CMOS technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
    — 15ns Maximum Propagation Delay
    — 75MHz Maximum Frequency
    — 6.5ns Maximum Clock to Output Delay
    — TTL Compatible 16mA Outputs
    — UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
    — 90mA Typical Icc
• E2 CELL TECHNOLOGY
    — Reconfigurable Logic
    — Reprogrammable Cells
    — 100% Tested/100% Yields
    — High Speed Electrical Erasure (<100ms)
    — 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
    — 78 x 64 x 36 FPLA Architecture
    — 10 Output Logic Macrocells
    — 8 Buried Logic Macrocells
    — 20 Input and I/O Logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
    — Asynchronous or Synchronous Clocking
    — Separate State Register and Input Clock Pins
    — Functional Superset of Existing 24-pin PAL®
    and FPLA Devices
• APPLICATIONS INCLUDE:
    — Sequencers
    — State Machine Control
    — Multiple PLD Device Integration

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.
   
FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices
        for 100% routability and 100% pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — programmable polarity
    — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides High-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
    — Supports HDL design methodologies with results optimized
        for ispMACH 4A
    — Flexibility to adapt to user requirements
    — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
    — LatticePROTM software for in-system programmability support
        on PCs and automated test equipment
    — Programming support on all major programmers
        including Data I/O, BP Microsystems, Advin,
        and System General
   

GENERAL DESCRIPTION
The MACH111 is a member of Vantis’ High-performance EE CMOS MACH 1 & 2 families. This device has approximately three times the logic macrocell capability of the popular PALCE22V10 without loss of speed.

DISTINCTIVE CHARACTERISTICS
◆ 44 Pins in PLCC and TQFP
◆ 32 Macrocells
◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial
◆ 182 MHz fCNT
◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
◆ 32 Flip-flops; 4 clock choices
◆ 2 “PALCE26V16” blocks
◆ SpeedLocking™ for guaranteed fixed timing
◆ Bus-Friendly™ Inputs and I/Os
◆ Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12)
◆ programmable power-down mode
◆ Safe for mixed supply voltage system designs
◆ Pin-compatible with the MACH211