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Part Name(s) : 74VHC373 74VHC373MTR 74VHC373TTR ST-Microelectronics
STMicroelectronics
Description : OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING View

DESCRIPTION
The 74VHC373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-TYPE LATCH are controlled by a LATCH enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q OUTPUTS will follow the data input precisely. When the LE is taken low, the Q OUTPUTS will be LATCHed precisely at the logic level of D input data. While the (OE) input is low, the 8 OUTPUTS will be in a normal logic STATE (high or low logic level) and while (OE) is in high level, the OUTPUTS will be in a high impedance STATE.
Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs WITH no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and OUTPUTS are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28% VCC (MIN.)
■ POWER DOWN PROTECTION ON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)

Part Name(s) : 74LVQ373M 74LVQ373_99 74LVQ373T ST-Microelectronics
STMicroelectronics
Description : OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING View

DESCRIPTION
The LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications.
These 8 bit D-TYPE LATCHs are controlled by a LATCH enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q OUTPUTS will follow the data input precisely.
When the LE is taken low, the Q OUTPUTS will be LATCHed precisely at the logic level of D input data. While the (OE) input is low, the 8 OUTPUTS will be in a normal logic STATE (high or low logic level) and while high level the OUTPUTS will be in a high impedance STATE.
It has better speed performance at 3.3V than 5V LS-TTL family combined WITH the true CMOS low power consuption.
All inputs and OUTPUTS are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ LOW NOISE: VOLP = 0.4V(TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE OUTPUT DRIVE CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY

Part Name(s) : 74LVQ373 74LVQ373MTR 74LVQ373TTR ST-Microelectronics
STMicroelectronics
Description : LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING View

DESCRIPTION
The 74LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
These 8 bit D-TYPE LATCH are controlled by a LATCH enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q OUTPUTS will follow the data input precisely.
When the LE is taken low, the Q OUTPUTS will be LATCHed precisely at the logic level of D input data. While the (OE) input is low, the 8 OUTPUTS will be in a normal logic STATE (high or low logic level) and while high level the OUTPUTS will be in a high impedance STATE.
All inputs and OUTPUTS are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.8 ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.4V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE OUTPUT DRIVE CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY

Part Name(s) : 74VHC573 74VHC573MTR 74VHC573M 74VHC573TTR 74VHC573T ST-Microelectronics
STMicroelectronics
Description : OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING View

DESCRIPTION
The 74VHC573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology.

■ HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
■ POWER DOWN PROTECTION ON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V (MAX.)


Part Name(s) : 74LVQ573_04 74LVQ573MTR_04 74LVQ573TTR_04 ST-Microelectronics
STMicroelectronics
Description : LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING View

DESCRIPTION
The 74LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
All inputs and OUTPUTS are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.8 ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.5V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY

Part Name(s) : 74HC563 74HC563D 74HC563DB 74HC563DW 74HC563N 74HC563U 74HCT563 74HCT563D 74HCT563DB 74HCT563DW Philips
Philips Electronics
Description : OCTAL D-TYPE transparent LATCH; 3-STATE; INVERTING View

GENERAL DESCRIPTION

The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible WITH low power Schottky TTL (LSTTL). They are specified in compliance WITH JEDEC standard no.7A.

The 74HC/HCT563 are OCTAL D-TYPE transparent LATCHes featuring separate D-TYPE inputs for each LATCH

and INVERTING 3-STATE OUTPUTS for bus oriented applications. A LATCH enable (LE) input and an

output enable (OE) input are common to all LATCHes.



FEATURES

• 3-STATE INVERTING OUTPUTS for bus oriented applications

• Inputs and OUTPUTS on opposite sides of package allowing easy interface WITH microprocessor

• Common 3-STATE output enable input

• Output capability: bus driver

• ICC category: MSI


Part Name(s) : 74LVQ573M_01 74LVQ573_01 74LVQ573MTR 74LVQ573TTR ST-Microelectronics
STMicroelectronics
Description : LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING View

DESCRIPTION
The 74LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
All inputs and OUTPUTS are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   tPD = 5.8 ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
   VOLP = 0.5V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY

Part Name(s) : SN74LS373 SN74LS373DW SN74LS373DWR2 SN74LS373H SN74LS373M SN74LS373MEL SN74LS373ML1 SN74LS373ML2 SN74LS373MR1 SN74LS373N ON-Semiconductor
ON Semiconductor
Description : OCTAL Transparent LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE Flip-Flop WITH 3-STATE OUTPUT View

OCTAL Transparent LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE Flip-Flop WITH 3-STATE Output



The SN74LS373 consists of eight LATCHes WITH 3-STATE OUTPUTS for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when LATCH Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is LATCHed. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance STATE.

The SN74LS374 is a high-speed, low-power OCTAL D-TYPE Flip-Flop featuring separate D-TYPE inputs for each flip-flop and 3-STATE OUTPUTS for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible WITH all ON Semiconductor TTL families.



•Eight LATCHes in a Single Package

•3-STATE OUTPUTS for Bus Interfacing

•Hysteresis on LATCH Enable

•Edge-Triggered D-TYPE Inputs

•Buffered Positive Edge-Triggered Clock

•Hysteresis on Clock Input to Improve Noise Margin

•Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : 74VHCT373AM 74VHCT373AT 74VHCT373A_99 ST-Microelectronics
STMicroelectronics
Description : OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING View

DESCRIPTION
The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology.
This 8 bit D-TYPE LATCH is controlled by a LATCH enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q OUTPUTS will follow the data inputs precisely. When the LE is taken low, the Q OUTPUTS will be LATCHed precisely at the logic level of D input data. While the (OE) input is low, the 8 OUTPUTS will be in a normal logic STATE (high or low logic level) and while high level the OUTPUTS will be in a high impedance STATE.
Power down protection is provided on all inputs and OUTPUTS and 0 to 7V can be accepted on inputs WITH no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and OUTPUTS are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ COMPATIBLEWITH TTL OUTPUTS:
   VIH = 2V (MIN), VIL = 0.8V(MAX)
■ POWERDOWN PROTECTIONON INPUTS & OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.9V(Max.)

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