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Part Name(s) : 74LS377 DM74LS377 DM74LS377N DM74LS377NX DM74LS377WM DM74LS377WMX Fairchild
Fairchild Semiconductor
Description : Octal D-Type Flip-Flop with Common Enable and Clock View

General Description

The DM74LS377 is an 8-bit register built using advanced low power Schottky technology. This register consists of eight D-Type Flip-Flops with a buffered Common Clock and a buffered Common input Enable. The device is packaged in the space-saving (0.3 inch row spacing) 20-pin package.



Features

■8-bit high speed parallel registers

■Positive edge-triggered D-Type Flip-Flops

■Fully buffered Common Clock and Enable inputs


Part Name(s) : 54LS377 54LS378 54LS379 74LS377 74LS378 74LS379 SN54LS377 SN54LS377J SN54LS378 SN54LS378J Motorola
Motorola => Freescale
Description : Octal D Flip-Flop with Enable; HEX D Flip-Flop with Enable; 4-BIT D Flip-Flop with Enable View

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-Type Flip-Flops with a buffered Common Clock and a buffered Common Clock Enable. The SN54/74LS378 is a 6-Bit Register with a buffered Common Enable.
This device is similar to the SN54/74LS174, but with Common Enable rather than Common Master Reset. The SN54/74LS379 is a 4-Bit Register with buffered Common Enable.
This device is similar to the SN54/74LS175 but features the Common Enable rather then Common Master Reset.

• 8-Bit High Speed Parallel Registers
• Positive Edge-Triggered D-Type Flip Flops
• Fully Buffered Common Clock and Enable Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects

Part Name(s) : 74AC11377D 74AC11377N 74AC11377 74ACT11377D 74ACT11377N Philips
Philips Electronics
Description : Octal D-Type flip flop with Enable View

Octal D-Type flip flop with Enable

Part Name(s) : 74ABT377 74ABT377CSC 74ABT377CSJ 74ABT377CMSA 74ABT377CMTC 74ABT377CSCX 74ABT377CSJX 74ABT377CMSAX 74ABT377CMTCX Fairchild
Fairchild Semiconductor
Description : Octal D-Type Flip-Flop with Clock Enable View

General Description
The ABT377 has eight edge-triggered, D-Type Flip-Flops with individual D inputs and Q outputs. The Common buffered Clock (CP) input loads all Flip-Flops simultaneously when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH Clock transition, is transferred to the corresponding Flip-Flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH Clock transition for predictable operation.

Features
Clock Enable for address and data synchronization applications
■ Eight edge-triggered D-Type Flip-Flops
■ Buffered Common Clock
■ See ABT273 for master reset version
■ See ABT373 for transparent latch version
■ See ABT374 for 3-STATE version
■ Output sink capability of 64 mA, source capability of 32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
   power up and power down cycle
■ Non-destructive hot insertion capability
■ Disable time less than Enable time to avoid bus contention


Part Name(s) : 74HCT377 74HC377 ETC1
Unspecified
Description : Octal D-Type Flip-Flop with DATA Enable POSITIVE EDGE TRIGGER View

Octal D-Type Flip-Flop with DATA Enable POSITIVE EDGE TRIGGER

Part Name(s) : MC74HC377A MC74HC377ADTG MC74HC377ADTR2G MC74HC377ADWG MC74HC377ADWR2G ON-Semiconductor
ON Semiconductor
Description : Octal D Flip-Flop with Common Clock and Enable View

High−Performance Silicon−Gate CMOS The MC74HC377A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip−flops with Common Clock and

Enable (E) inputs. Each flip−flop is loaded with a low−to−high transition of the Clock input. Enable (E) is active low.



Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 A

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 264 FETs or 66 Equivalent Gates

•These are Pb−Free Devices


Part Name(s) : 74AC377MTCX_NL 74AC377PC 74AC377PCX 74AC377_05 74ACT377_05 74AC377SC_05 74AC377SJ_05 74AC377MTC_05 74ACT377SC_05 74ACT377SJ_05 Fairchild
Fairchild Semiconductor
Description : Octal D-Type Flip-Flop with Clock Enable View

General Description The AC/ACT377 has eight edge-triggered, D-Type Flip-Flops with individual D inputs and Q outputs. The Common buffered Clock (CP) input loads all Flip-Flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH Clock transition, is transferred to the corresponding Flip-Flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH Clock transition for predictable operation.

Features
■ ICC reduced by 50%
■ Ideal for addressable register applications
Clock Enable for address and data synchronization applications
■ Eight edge-triggered D-Type Flip-Flops
■ Buffered Common Clock
■ Outputs source/sink 24 mA
■ See 273 for master reset version
■ See 373 for transparent latch version
■ See 374 for 3-STATE version
■ ACT377 has TTL-compatible inputs

Part Name(s) : 54FCT377 54FCT377DMQB 54FCT377FMQB 54FCT377LMQB 5962-87627012A 5962-8762701RA 5962-8762701SA National-Semiconductor
National ->Texas Instruments
Description : Octal D-Type Flip-Flop with Clock Enable View

General Description
The ’FCT377 has eight edge-triggered, D-Type Flip-Flops with individual D inputs and Q outputs. The Common buffered Clock (CP) input loads all Flip-Flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in put, one setup time before the LOW-to-HIGH Clock transi tion, is transferred to the corresponding Flip-Flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH Clock transition for predictable operation.

Features
Clock Enable for address and data synchronization applications
■ Eight edge-triggered D Flip-Flops
■ Buffered Common Clock
■ See ’FCT273 for master reset version
■ See ’FCT373 for transparent latch version
■ See ’FCT374 for TRI-STATE® version
■ TTL input and output level compatible
■ CMOS power consumption
■ Output sink capability of 32 mA, source capability of 12 mA
■ Standard Microcircuit Drawing (SMD) 5962-8762701

Part Name(s) : MC74AC374DW MC74AC374N MC74ACT374DW MC74ACT374N MC74AC374 MC74ACT374 Motorola
Motorola => Freescale
Description : Octal D-Type Flip-Flop with 3-State Outputs View

Octal D-Type Flip-Flop with 3-State Outputs

The MC74AC374/74ACT374 is a high-speed, low-power Octal D-Type Flip-Flop featuring separate D-Type inputs for each Flip-Flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) are Common to all Flip-Flops.

• Buffered Positive Edge-Triggered Clock
• 3-State Outputs for Bus-Oriented Applications
• Outputs Source/Sink 24 mA
• See MC74AC273 for Reset Version
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC574 for Broadside Pinout Version
• See MC74AC564 for Broadside Pinout Version with Inverted Outputs
• ′ACT374 Has TTL Compatible Inputs

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