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Part Name(s) : SN74LS373 SN74LS373DW SN74LS373DWR2 SN74LS373H SN74LS373M SN74LS373MEL SN74LS373ML1 SN74LS373ML2 SN74LS373MR1 SN74LS373N ON-Semiconductor
ON Semiconductor
Description : Octal Transparent Latch with 3-STATE Outputs; Octal D-Type Flip-Flop with 3-STATE OUTPUT View

Octal Transparent Latch with 3-STATE Outputs; Octal D-Type Flip-Flop with 3-STATE Output



The SN74LS373 consists of eight Latches with 3-STATE Outputs for bus organized system applications. The flip-flops appear Transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance state.

The SN74LS374 is a high-speed, low-power Octal D-Type Flip-Flop featuring separate D-Type inputs for each flip-flop and 3-STATE Outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.



•Eight Latches in a Single Package

3-STATE Outputs for Bus Interfacing

•Hysteresis on Latch Enable

•Edge-Triggered D-Type Inputs

•Buffered Positive Edge-Triggered Clock

•Hysteresis on Clock Input to Improve Noise Margin

•Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : SN54LS373 SN54LS373J SN54LS374 SN54LS374J SN74LS373 SN74LS373DW SN74LS373N SN74LS374 SN74LS374DW SN74LS374N Motorola
Motorola => Freescale
Description : Octal Transparent Latch with 3-STATE Outputs View

Octal Transparent Latch with 3-STATE Outputs; Octal D-Type FLIP-FLOP with 3-STATE OUTPUT



The SN54 /74LS373 consists of eight Latches with 3-STATE Outputs for bus organized system applications. The flip-flops appear Transparent to the data (datachanges asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW,the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE)is LOW. When OEis HIGH the bus output is in

the high impedance state.

TheSN54/74LS374 is a high-speed, low-power Octal D-Type Flip-Flop fea turingseparate D-Type inputs for each flip-flop and 3-STATE Outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54/74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.



• Eight Latches in a Single Package

3-STATE Outputs for Bus Interfacing

• Hysteresis on Latch Enable

• Edge-Triggered D-Type Inputs

• Buffered Positive Edge-Triggered Clock

• Hysteresis on Clock Input to Improve Noise Margin

• Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : SN74HC573A-Q1 SN74HC573AQDWRQ1 SN74HC573AQPWRG4Q1 SN74HC573AQPWRQ1 HC573AQ TI
Texas Instruments
Description : Octal Transparent D-Type Latch with 3-STATE Outputs View

description/ordering information
This Octal Transparent D-Type Latch features 3-STATE Outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

● Qualified for Automotive Applications
● Wide Operating Voltage Range of 2 V to 6 V
● High-Current 3-STATE Outputs Drive Bus Lines Directly or up to 15 LSTTL Loads
● Low Power Consumption, 80-µA Max ICC
● Typical tpd = 21 ns
● ±6-mA Output Drive at 5 V
● Low Input Current of 1 µA Max
● Bus-Structured Pinout

Part Name(s) : HC573AQ SN74HC573A-Q1 SN74HC573AQPWRQ1 SN74HC573AQDWRQ1 SN74HC573AQPWRG4Q1 Texas-Instruments
Texas Instruments
Description : Octal Transparent D-Type Latch with 3-STATE Outputs View

description/ordering information
This Octal Transparent D-Type Latch features 3-STATE Outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

● Qualified for Automotive Applications
● Wide Operating Voltage Range of 2 V to 6 V
● High-Current 3-STATE Outputs Drive Bus Lines Directly or up to 15 LSTTL Loads
● Low Power Consumption, 80-µA Max ICC
● Typical tpd = 21 ns
● ±6-mA Output Drive at 5 V
● Low Input Current of 1 µA Max
● Bus-Structured Pinout


Part Name(s) : MC74AC373DTEL MC74AC373ML1 MC74AC373ML2 MC74AC373MR1 MC74AC373MR2 MC74AC373SD MC74AC373SDR2 MC74ACT373ML1 MC74ACT373ML2 MC74ACT373MR1 ON-Semiconductor
ON Semiconductor
Description : Octal Transparent Latch with 3 State Outputs View

Octal Transparent Latch with 3 State Outputs

The MC74AC373/74ACT373 consists of eight Latches with 3−state Outputs for bus organized system applications. The flip−flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH, the bus output is in the high impedance state.

Features
• Eight Latches in a Single Package
• 3−State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
•′ ACT373 Has TTL Compatible Inputs
• Pb−Free Packages are Available

Part Name(s) : MC54F373J MC74AC373 MC74AC373DW MC74AC373N MC74AC533DW MC74ACT373 MC74ACT373D MC74ACT373DW MC74ACT533N MC74F373N Motorola
Motorola => Freescale
Description : Octal Transparent Latch with 3 State Outputs View

Octal Transparent Latch with 3 State Outputs

The MC74AC373/74ACT373 consists of eight Latches with 3-STATE Outputs for bus organized system applications. The flip-flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

• Eight Latches in a Single Package
3-STATE Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
• ′ACT373 Has TTL Compatible Inputs

Part Name(s) : CD54AC373 CD54AC3733A CD54AC373A CD54AC373F3A CD54ACT373 CD54ACT3733A CD54ACT373A Intersil
Intersil
Description : Octal Transparent Latch Three-State, Non-Inverting View

Description

The CD54AC373/3A and CD54ACT373/3A are Octal Transparent three-state Latches that utilize the Harris Advanced CMOS Logic technology. The Outputs are Transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is Latched. The Output Enable (OE) controls the three-state Outputs. When the Out put Enable (OE) is HIGH, the Outputs are in the high-imped ance state. The Latch operation is independent of the state of the Output Enable.



 


Part Name(s) : CD74FCT373M96 TI
Texas Instruments
Description : BiCMOS Octal Transparent D-Type Latch with 3-STATE Outputs View

description
The CD74FCT373 is an Octal, Transparent, D-Type Latch with 3-STATE Outputs using a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.
   
● BiCMOS Technology with Low Quiescent
    Power
● Buffered Inputs
● Noninverted Outputs
● Input/Output Isolation From VCC
● 48-mA Output Sink Current
● Controlled Output Edge Rates
● Output Voltage Swing Limited to 3.7 V
● SCR Latch-Up-Resistant BiCMOS Process
    and Circuit Design
● Package Options Include Plastic
    Small-Outline (M) and Shrink Small-Outline
    (SM) Packages and Standard Plastic (E) DIP
   

Part Name(s) : SN74LVC573 SN74LVC573DB SN74LVC573DW SN74LVC573PW TI
Texas Instruments
Description : Octal Transparent D-Type Latch with 3-STATE Outputs View

description
This Octal Transparent D-Type Latch is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVC573 features 3-STATE Outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

• EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

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