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Part Name(s) : 54ACTQ533D 54ACTQ533F 54ACTQ533L 54ACTQ533 National-Semiconductor
National ->Texas Instruments
Description : Quiet Series Octal Transparent Latch with TRI-STATE® Outputs View

General Description
The ACTQ533 consists of eight Latches with TRI-STATE Outputs for bus organized system applications. The flip-flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ ICC and IOZ reduced by 50%
■ Guaranteed simultaneous switching noise level and dynamic threshold performance
■ Improved Latch up immunity
■ Eight Latches in a single package
■ TRI-STATE Outputs drive bus lines or buffer memory address registers
Outputs source/sink 24 mA
■ Inverted version of the ACTQ373
■ 4 kV minimum ESD immunity

Part Name(s) : 54FCT373 54FCT373DMQB 54FCT373FMQB 54FCT373LMQB 5962-87644012A 5962-8764401RA 5962-8764401SA National-Semiconductor
National ->Texas Instruments
Description : Octal Transparent Latch with TRI-STATE® Outputs View

General Description

The ’FCT373 consists of eight Latches with TRI-STATE Outputs for bus organized system applications. The flip-flops ap pear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.



Features

● TRI-STATE Outputs for bus interfacing

● TTL input and output level compatible

● CMOS power consumption

● Output sink capability of 32 mA, source capability of 12 mA

● Standard Microcircuit Drawing (SMD) 5962-8764401


Part Name(s) : 54ACTQ533DMQB 54ACTQ533FMQB 54ACTQ533LMQB National-Semiconductor
National ->Texas Instruments
Description : Octal Transparent Latch with 3-State Outputs View

General Description
The ACTQ533 consists of eight Latches with TRI-STATE Outputs for bus organized system applications. The flip-flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedancestate.

Features
- Icc and Ioz reduced by 50%
- Guaranteed simultaneous switching noise level and dynamic threshold performance
- Guaranteed pin-to-pin skew AC performance
- Improved Latch up immunity
- Eight Latches in a single package
- TRI-STATE Outputs drive bus lines or buffer memory address registers
- Outputs source/sink 24 mA
- 4 kV minimum ESD immunity

Part Name(s) : MC74AC373DTEL MC74AC373ML1 MC74AC373ML2 MC74AC373MR1 MC74AC373MR2 MC74AC373SD MC74AC373SDR2 MC74ACT373ML1 MC74ACT373ML2 MC74ACT373MR1 ON-Semiconductor
ON Semiconductor
Description : Octal Transparent Latch with 3 State Outputs View

Octal Transparent Latch with 3 State Outputs

The MC74AC373/74ACT373 consists of eight Latches with 3−state Outputs for bus organized system applications. The flip−flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH, the bus output is in the high impedance state.

Features
• Eight Latches in a Single Package
• 3−State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
•′ ACT373 Has TTL Compatible Inputs
• Pb−Free Packages are Available


Part Name(s) : SCAN18373T SCAN18373TMDA National-Semiconductor
National ->Texas Instruments
Description : Transparent Latch with TRI-STATE® Outputs View

General Description
The SCAN18373T is a high speed, low-power Transparent Latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented Latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).

Features
■ IEEE 1149.1 (JTAG) Compliant
■ Buffered active-low Latch enable
■ TRI-STATE Outputs for bus-oriented applications
■ 9-bit data busses for parity applications
■ Reduced-swing Outputs source 24 mA/sink 48 mA
■ Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V
■ TTL compatible inputs
■ 25 mil pitch Cerpack packaging
■ Includes CLAMP and HIGHZ instructions
■ Standard Microcircuit Drawing (SMD) 5962-9311801

Part Name(s) : SN74LS373 SN74LS373DW SN74LS373DWR2 SN74LS373H SN74LS373M SN74LS373MEL SN74LS373ML1 SN74LS373ML2 SN74LS373MR1 SN74LS373N ON-Semiconductor
ON Semiconductor
Description : Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-STATE OUTPUT View

Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output



The SN74LS373 consists of eight Latches with 3-state Outputs for bus organized system applications. The flip-flops appear Transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance state.

The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state Outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.



•Eight Latches in a Single Package

•3-State Outputs for Bus Interfacing

•Hysteresis on Latch Enable

•Edge-Triggered D-Type Inputs

•Buffered Positive Edge-Triggered Clock

•Hysteresis on Clock Input to Improve Noise Margin

•Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : SN54LS373 SN54LS373J SN54LS374 SN54LS374J SN74LS373 SN74LS373DW SN74LS373N SN74LS374 SN74LS374DW SN74LS374N Motorola
Motorola => Freescale
Description : Octal Transparent Latch with 3-state Outputs View

Octal Transparent Latch with 3-STATE Outputs; Octal D-TYPE FLIP-FLOP with 3-STATE OUTPUT



The SN54 /74LS373 consists of eight Latches with 3-state Outputs for bus organized system applications. The flip-flops appear Transparent to the data (datachanges asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW,the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE)is LOW. When OEis HIGH the bus output is in

the high impedance state.

TheSN54/74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea turingseparate D-type inputs for each flip-flop and 3-state Outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54/74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.



• Eight Latches in a Single Package

• 3-State Outputs for Bus Interfacing

• Hysteresis on Latch Enable

• Edge-Triggered D-Type Inputs

• Buffered Positive Edge-Triggered Clock

• Hysteresis on Clock Input to Improve Noise Margin

• Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : CD54AC373 CD54AC3733A CD54AC373A CD54AC373F3A CD54ACT373 CD54ACT3733A CD54ACT373A Intersil
Intersil
Description : Octal Transparent Latch Three-State, Non-Inverting View

Description

The CD54AC373/3A and CD54ACT373/3A are Octal Transparent three-state Latches that utilize the Harris Advanced CMOS Logic technology. The Outputs are Transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is Latched. The Output Enable (OE) controls the three-state Outputs. When the Out put Enable (OE) is HIGH, the Outputs are in the high-imped ance state. The Latch operation is independent of the state of the Output Enable.



 


Part Name(s) : 54ACQ373 54ACQ373D 54ACQ373F 54ACQ373L 54ACTQ373 54ACTQ373D 54ACTQ373F 54ACTQ373L 5962-92178 5962-92188 National-Semiconductor
National ->Texas Instruments
Description : Quiet Series Octal Transparent Latch with TRI-STATE® Outputs View

General Description
The ’ACQ/’ACTQ374 is a high-speed, low-power Octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE Outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.

Features
■ ICC and IOZ reduced by 50%
■ Guaranteed simultaneous switching noise level and dynamic threshold performance
■ Improved Latch-up immunity
■ Buffered positive edge-triggered clock
■ TRI-STATE Outputs drive bus lines or buffer memory address registers
Outputs source/sink 24 mA
■ Faster prop delays than the standard ’AC/’ACT374
■ 4 kV minimum ESD immunity
■ Standard Military Drawing (SMD)
    — ’ACTQ374: 5962-92189
    — ’ACQ374: 5962-92179

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