Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

P/N + Description + Content Search

Search Word's :
Description : Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-STATE OUTPUT

Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output



The SN74LS373 consists of eight Latches with 3-state Outputs for bus organized system applications. The flip-flops appear Transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance state.

The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state Outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.



•Eight Latches in a Single Package

•3-State Outputs for Bus Interfacing

•Hysteresis on Latch Enable

•Edge-Triggered D-Type Inputs

•Buffered Positive Edge-Triggered Clock

•Hysteresis on Clock Input to Improve Noise Margin

•Input Clamp Diodes Limit High Speed Termination Effects


Description : Octal Transparent Latch with 3 State Outputs

Octal Transparent Latch with 3 State Outputs

The MC74AC373/74ACT373 consists of eight Latches with 3-state Outputs for bus organized system applications. The flip-flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
• ′ACT373 Has TTL Compatible Inputs

Description : Octal Transparent Latch with 3-State Outputs

Octal Transparent Latch with 3-State Outputs

The MC74AC533/74ACT533 consists of eight Latches with 3-state Outputs for bus organized system applications. The flip-flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The ′AC/ACT533 is the same as the ′AC/ACT373, except that the Outputs are inverted. For description and logic diagram please see the ′AC/ACT373 data sheet.

• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• ′ACT533 Has TTL Compatible Inputs
• Inverted Output Version of ′ACT373

Description : Octal Transparent Latch with 3 State Outputs

Octal Transparent Latch with 3 State Outputs

The MC74AC373/74ACT373 consists of eight Latches with 3−state Outputs for bus organized system applications. The flip−flops appear Transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is Latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH, the bus output is in the high impedance state.

Features
• Eight Latches in a Single Package
• 3−State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
•′ ACT373 Has TTL Compatible Inputs
• Pb−Free Packages are Available

Description : Octal Transparent Latch Three-State, Non-Inverting

Description

The CD54AC373/3A and CD54ACT373/3A are Octal Transparent three-state Latches that utilize the Harris Advanced CMOS Logic technology. The Outputs are Transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is Latched. The Output Enable (OE) controls the three-state Outputs. When the Out put Enable (OE) is HIGH, the Outputs are in the high-imped ance state. The Latch operation is independent of the state of the Output Enable.



 


Description : Octal Transparent Latch with 3-state Outputs

Octal Transparent Latch with 3-STATE Outputs; Octal D-TYPE FLIP-FLOP with 3-STATE OUTPUT



The SN54 /74LS373 consists of eight Latches with 3-state Outputs for bus organized system applications. The flip-flops appear Transparent to the data (datachanges asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW,the data that meets the setup times is Latched. Data appears on the bus when the Output Enable (OE)is LOW. When OEis HIGH the bus output is in

the high impedance state.

TheSN54/74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea turingseparate D-type inputs for each flip-flop and 3-state Outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54/74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.



• Eight Latches in a Single Package

• 3-State Outputs for Bus Interfacing

• Hysteresis on Latch Enable

• Edge-Triggered D-Type Inputs

• Buffered Positive Edge-Triggered Clock

• Hysteresis on Clock Input to Improve Noise Margin

• Input Clamp Diodes Limit High Speed Termination Effects


Description : Octal Transparent Latch (3-State), Octal D flip-flop (3-State)

DESCRIPTION

The 74F373 is an Octal Transparent Latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates.



FEATURES

• 8-bit Transparent Latch — 74F373

• 8-bit positive edge triggered register — 74F374

• 3-State Outputs glitch free during power-up and power-down

• Common 3-State output register

• Independent register and 3-State buffer operation

• SSOP Type II Package



 


IKSEMICON
IK Semicon Co., Ltd
Description : Octal 3-State Inverting Transparent Latch

Octal 3-State Inverting Transparent Latch
High-Performance Silicon-Gate CMOS

The IN74HC533A is identical in pinout to the LS/ALS533. The device inputs are compatible with standard CMOS Outputs; with pullup resistors, they are compatible with LS/ALSTTL Outputs.
These Latches appear Transparent to data (i.e., the Outputs change asynchronously) when Latch Enable is high. The data appears as the Outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes Latched.
The Output Enable input does not affect the state of the Latches, but when Output Enable is high, all device Outputs are forced to the high impedance state. Thus, data may be Latched even when the Outputs are not enabled.

Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

Description : 74F373 Octal Transparent Latch (3-State) 74F374 Octal D flip-flop (3-State)

DESCRIPTION
The 74F373 is an Octal Transparent Latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates.

FEATURES
• 8-bit Transparent Latch — 74F373
• 8-bit positive edge triggered register — 74F374
• 3-State Outputs glitch free during power-up and power-down
• Common 3-State output register
• Independent register and 3-State buffer operation
• SSOP Type II Package

Description : Octal D-type Transparent Latch (3-State)

DESCRIPTION
The 74AC573/74ACT573 is an Octal D-type Transparent Latch featuring separate D-type inputs for each Latch and 3-State Outputs for bus oriented applications.

12345678910 Next



All Rights Reserved© datasheetq.com  [Privacy Policy ] [ Request Datasheet] [Contact Us]