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Part Name(s) : 74AC11379 74AC11379D 74AC11379N 74ACT11379 74ACT11379D 74ACT11379N Philips
Philips Electronics
Description : Quad D-type flip flop with data enable View

Quad D-type flip flop with data enable

Part Name(s) : 74HCT377 74HC377 ETC1
Unspecified
Description : OCTAL D-type flip-flop with data enable POSITIVE EDGE TRIGGER View

OCTAL D-type flip-flop with data enable POSITIVE EDGE TRIGGER

Part Name(s) : 74AC175CW 74ACT175CW 74ACT175PC Fairchild
Fairchild Semiconductor
Description : Quad D-type flip-flop View

The 74AC175/74ACT175 (AC/ACT175) is a high-speed Quad D-type flip-flop.



The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.



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Part Name(s) : 54LS377 54LS378 54LS379 74LS377 74LS378 74LS379 SN54LS377 SN54LS377J SN54LS378 SN54LS378J Motorola
Motorola => Freescale
Description : OCTAL D flip-flop with enable; HEX D flip-flop with enable; 4-BIT D flip-flop with enable View

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable.
This device is similar to the SN54/74LS174, but with common enable rather than common Master Reset. The SN54/74LS379 is a 4-Bit Register with buffered common enable.
This device is similar to the SN54/74LS175 but features the common enable rather then common Master Reset.

• 8-Bit High Speed Parallel Registers
• Positive Edge-Triggered D-type flip flops
• Fully Buffered Common Clock and enable Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects


Part Name(s) : 74AC11377D 74AC11377N 74AC11377 74ACT11377D 74ACT11377N Philips
Philips Electronics
Description : Octal D-type flip flop with enable View

Octal D-type flip flop with enable

Part Name(s) : 74AHC377 74AHC377D 74AHC377PW 74AHCT377 74AHCT377D 74AHCT377PW NXP
NXP Semiconductors.
Description : Octal D-type flip-flop with data enable; positive-edge trigger View

General description
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.

For versions associated with the 74AHC377; 74AHCT377, refer to the following:

• For the master reset version, see 74AHC273; 74AHCT273
• For the transparent latch version, see 74AHC373; 74AHCT373
• For the 3-state version, see 74AHC374; 74AHCT374

Features
■ Balanced propagation delays
■ All inputs have Schmitt-trigger actions
■ Inputs accept voltages higher than VCC
■ Ideal for addressable register applications
data enable for address and data synchronization
■ Eight positive-edge triggered D-type flip-flops
■ Input levels:
   ♦ For 74AHC377: CMOS level
   ♦ For 74AHCT377: TTL level
■ ESD protection:
   ♦ HBM EIA/JESD22-A114E exceeds 2000 V
   ♦ MM EIA/JESD22-A115-A exceeds 200 V
   ♦ CDM EIA/JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

Part Name(s) : 74AC11378 74ACT11378 74AC11378D 74ACT11378D 74AC11378N 74ACT11378N Philips
Philips Electronics
Description : Hex D-type flip-flop with enable, positive edge trigger View

Hex D-type flip-flop with enable, positive edge trigger

Part Name(s) : CD40174BC CD40174BCM CD40175BCM CD40175BCN MC14174B MC14175B MM74C175 CD40174BCMX CD40174BCN CD40175BC Fairchild
Fairchild Semiconductor
Description : Hex D-type flip-flop Quad D-type flip-flop View

General Description
The CD40174BC consists of six positive-edge triggered D type flip-flops; the true outputs from each flip-flop are externally available. The CD40175BC consists of four positive edge triggered D-type flip-flops; both the true and comple ment outputs from each flip-flop are externally available.
All flip-flops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all
Q outputs to logical “0” and Qs (CD40175BC only) to logical “1”. All inputs are protected from static discharge by diode clamps to VDDand VSS.

Features
■ Wide supply voltage range: 3V to 15V
■ High noise immunity: 0.45 VDD(typ.)
■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS
■ Equivalent to MC14174B, MC14175B
■ Equivalent to MM74C174, MM74C175

Part Name(s) : 74F175 74F175PC 74F175SC 74F175SCX 74F175SJ 74F175SJX Fairchild
Fairchild Semiconductor
Description : Quad D-type flip-flop View

General Description
The 74F175 is a high-speed Quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, LOW.

Features
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ True and complement output

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