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Part Name(s) : SN74HC00AN-P SN74HC00A TI
Texas Instruments
Description : Quadruple 2 - INPUT POSITIVE - NAND Gates View

Quadruple 2 - INPUT POSITIVE - NAND Gates

Part Name(s) : HD74LS26 Hitachi
Hitachi -> Renesas Electronics
Description : Quadruple 2-Input High-voltage Interface Positive NAND Gates View

Quadruple 2-Input High-voltage Interface Positive NAND Gates

Part Name(s) : HD74LS26 HD74LS26P HD74LS26FPEL Renesas
Renesas Electronics
Description : Quadruple 2-Input High-voltage Interface Positive NAND Gates View

Quadruple 2-Input High-voltage Interface Positive NAND Gates

Part Name(s) : HD74LS03 HD74LS03FPEL HD74LS03P Renesas
Renesas Electronics
Description : Quadruple 2-Input Positive NAND Gates (with Open Collector Outputs) View

Quadruple 2-Input Positive NAND Gates (with Open Collector Outputs)


Part Name(s) : HD74LS132FP HD74LS132FPEL HD74LS132P HD74LS132RP HD74LS132RPEL HD74LS132 Renesas
Renesas Electronics
Description : Quadruple 2-Input Positive NAND Schmitt-triggers View

Quadruple 2-Input Positive NAND Schmitt-triggers

Part Name(s) : HD74LS09 HD74LS09P HD74LS09FPEL Renesas
Renesas Electronics
Description : Quadruple 2-Input Positive AND Gates (with Open Collector Outputs) View

Quadruple 2-Input Positive AND Gates (with Open Collector Outputs)

Part Name(s) : HD74LS20 HD74LS20FPEL HD74LS20P HD74LS20RPEL Renesas
Renesas Electronics
Description : Dual 4-input Positive NAND Gates View

Dual 4-input Positive NAND Gates

Part Name(s) : SN54LV00 SN54LV00FK SN54LV00J SN54LV00W SN74LV00 SN74LV00D SN74LV00DB SN74LV00DBLE SN74LV00DR SN74LV00PW TI
Texas Instruments
Description : Quadruple 2-Input Positive-NAND Gates View

description

These Quadruple 2-Input Positive-NAND Gates are designed for 2.7-V to 5.5-V VCCoperation.



EPIC™ (Enhanced-Performance Implanted CMOS) 2-µ Process

Typical VOLP(Output Ground Bounce) < 0.8 V at VCC, TA= 25°C

Typical VOHV(Output VOHUndershoot) > 2 V at VCC, TA= 25°C

ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17

Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs


Part Name(s) : HD74LS12 HD74LS12P Renesas
Renesas Electronics
Description : Triple 3-input Positive NAND Gates (with Open Collector Output) View

Triple 3-input Positive NAND Gates (with Open Collector Output)


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