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Part Name(s) : 74ALS74
Fairchild
Fairchild Semiconductor
Description : Dual D POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR

General Description

The DM74ALS74A contains two independent positive edge-triggered FLIP-FLOPs. Each FLIP-FLOP has individual D, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs.

Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.

Asynchronous PRESET AND CLEAR inputs will set or CLEAR Q output respectively upon the application of low level signal.



Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full temperature AND VCC range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally AND pin-for-pin compatible WITH Schottky AND LS TTL counterpart

■ Improved AC performance over LS74 at approximately half the power



 


Description : Dual D POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR

General Description
The DM74ALS74A contains two independent positive edge-triggered FLIP-FLOPs. Each FLIP-FLOP has individual D, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs.
Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.
Asynchronous PRESET AND CLEAR inputs will set or CLEAR Q output respectively upon the application of low level signal.

Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full temperature AND VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL process
■ Functionally AND pin-for-pin compatible WITH Schottky AND LS TTL counterpart
■ Improved AC performance over LS74 at approximately half the power

Fairchild
Fairchild Semiconductor
Description : Dual D-TYPE POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR

General Description

The AS74 is a dual edge-triggered FLIP-FLOPs. Each FLIP-FLOP has individual D, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.



Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full temperature AND VCC range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally AND pin-for-pin compatible WITH Schottky AND LS TTL counterpart

■ Improved AC performance over S74 at approximately half the power


Fairchild
Fairchild Semiconductor
Description : Dual POSITIVE-EDGE-TRIGGEred J-K FLIP-FLOP WITH PRESET, CLEAR, AND Complementary Outputs

General Description
This device contains two independent POSITIVE-EDGE-TRIGGEred J-K FLIP-FLOPs WITH complementary outputs. The J AND K data is accepted by the FLIP-FLOP on the rising edge of the clock pulse. The triggering occurs at a voltage level AND is not directly related to the transition time of the rising edge of the clock. The data on the J AND K inputs may be changed while the clock is HIGH or LOW as long as setup AND hold times are not violated. A low logic level on the PRESET or CLEAR inputs will set or reset the outputs regard less of the logic levels of the other inputs.

Part Name(s) : DM7474 DM7474N
Fairchild
Fairchild Semiconductor
Description : Dual POSITIVE-EDGE-TRIGGEred D-TYPE FLIP-FLOPs WITH PRESET, CLEAR AND Complementary Outputs

General Description

This device contains two independent POSITIVE-EDGE-TRIGGEred D-TYPE FLIP-FLOPs WITH complementary outputs. The information on the D input is accepted by the FLIP-FLOPs on the positive going edge of the clock pulse. The triggering occurs at a voltage level AND is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH WITHout affecting the outputs as long as the data setup AND hold times are not violated. A LOW logic level on the PRESET or CLEAR inputs will set or reset the outputs regardless of the logic levels of the other inputs.


Description : DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY



TheSN54/74LS74A dual edge-triggered FLIP-FLOP utilizesSchottky TTL circuitryto produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP hasindividual CLEAR AND set inputs, AND also complementary Q AND Qoutputs.



Informationat input D is transferred to the Q output on thepositive-going edgeof the clock pulse. Clock triggering occursat a voltage level of the clock pulseAND is not directly related to the transition time of the positive-going pulse.When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.




Description : Dual J-K POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR

General Description
The DM74ALS109A is a dual edge-triggered FLIP-FLOP. Each FLIP-FLOP has individual J, K, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs.
   
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full
    temperature AND VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
    process
■ Functionally AND pin for pin compatible WITH Schottky
    AND LS TTL counterpart
■ Improved AC performance over LS109 at approximately
    half the power
   

Motorola
Motorola => Freescale
Description : DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS74A dual edge-triggered FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP has individual CLEAR AND set inputs, AND also complementary Q AND Q outputs.
Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

ONSEMI
ON Semiconductor
Description : Dual D−Type Positive Edge−Triggered Flip−Flop

The SN74LS74A dual edge-triggered FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP has individual CLEAR AND set inputs, AND also complementary Q AND Q outputs.

Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
   

Fairchild
Fairchild Semiconductor
Description : Dual POSITIVE-EDGE-TRIGGEred D FLIP-FLOPs WITH PRESET, CLEAR, AND Complementary Outputs

General Description

This device contains two independent POSITIVE-EDGE-TRIGGEred D FLIP-FLOPs WITH complementary outputs. The information on the D input is accepted by the FLIP-FLOPs on the positive going edge of the clock pulse. The triggering occurs at a voltage level AND is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH WITHout affecting the outputs as long as setup AND hold times are not violated. A low logic level on the PRESET or CLEAR inputs will set or reset the outputs regardless of the logic levels of the other inputs.


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